diff options
Diffstat (limited to 'util')
| -rw-r--r-- | util/msrtool/intel_atom.c | 6 | ||||
| -rw-r--r-- | util/msrtool/intel_core2_later.c | 6 | ||||
| -rw-r--r-- | util/msrtool/intel_nehalem.c | 6 |
3 files changed, 9 insertions, 9 deletions
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 2d89c9c640..39e1676e96 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -176,13 +176,13 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index ad353ebc0c..b61f508b4f 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -1057,13 +1057,13 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 679efb5f1c..6f99217f1e 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -1621,13 +1621,13 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { |