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-rw-r--r--util/inteltool/gpio.c3
-rw-r--r--util/inteltool/inteltool.c22
-rw-r--r--util/inteltool/inteltool.h49
-rw-r--r--util/inteltool/memory.c2
-rw-r--r--util/inteltool/powermgt.c49
5 files changed, 102 insertions, 23 deletions
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index fe8481e2fb..b4f11691dd 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -131,6 +131,9 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_82371XX:
+ printf("This southbridge has GPIOs in the PM unit.\n");
+ return 1;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have GPIOBASE.\n");
return 1;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 827ce29b48..4f0b9cd9b9 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -29,6 +29,9 @@ static const struct {
uint16_t vendor_id, device_id;
char *name;
} supported_chips_list[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
@@ -47,7 +50,8 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" }
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
};
#ifndef __DARWIN__
@@ -112,7 +116,7 @@ void print_usage(const char *name)
int main(int argc, char *argv[])
{
struct pci_access *pacc;
- struct pci_dev *sb, *nb;
+ struct pci_dev *sb = NULL, *nb, *dev;
int i, opt, option_index = 0;
unsigned int id;
@@ -204,8 +208,20 @@ int main(int argc, char *argv[])
pci_scan_bus(pacc);
/* Find the required devices */
+ for (dev = pacc->devices; dev; dev = dev->next) {
+ pci_fill_info(dev, PCI_FILL_CLASS);
+ /* The ISA/LPC bridge can be 0x1f, 0x07, or 0x04 so we probe. */
+ if (dev->device_class == 0x0601) { /* ISA/LPC bridge */
+ if (sb == NULL)
+ sb = dev;
+ else
+ fprintf(stderr, "Multiple devices with class ID"
+ " 0x0601, using %02x%02x:%02x.%02x\n",
+ dev->domain, dev->bus, dev->dev,
+ dev->func);
+ }
+ }
- sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
if (!sb) {
printf("No southbridge found.\n");
exit(1);
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 7f9c59d96b..b4757e53e8 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -32,27 +32,36 @@
#define INTELTOOL_VERSION "1.0"
/* Tested chipsets: */
-#define PCI_VENDOR_ID_INTEL 0x8086
-#define PCI_DEVICE_ID_INTEL_ICH 0x2410
-#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
-#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
-#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
-#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
-#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
-#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
-#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
-#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
-#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
-#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
+#define PCI_VENDOR_ID_INTEL 0x8086
+#define PCI_DEVICE_ID_INTEL_ICH 0x2410
+#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
+#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
+#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
+#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
+#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
+#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
+#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815
+#define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16
-#define PCI_DEVICE_ID_INTEL_82810 0x7120
-#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
-#define PCI_DEVICE_ID_INTEL_82845 0x1a30
-#define PCI_DEVICE_ID_INTEL_82945P 0x2770
-#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
-#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
-#define PCI_DEVICE_ID_INTEL_82975X 0x277c
-#define PCI_DEVICE_ID_INTEL_X58 0x3405
+#define PCI_DEVICE_ID_INTEL_82810 0x7120
+#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
+#define PCI_DEVICE_ID_INTEL_82845 0x1a30
+#define PCI_DEVICE_ID_INTEL_82945P 0x2770
+#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
+#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
+#define PCI_DEVICE_ID_INTEL_82975X 0x277c
+#define PCI_DEVICE_ID_INTEL_X58 0x3405
+
+#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
+
+/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
+#define PCI_DEVICE_ID_INTEL_82443BX 0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP 0x7192
+
+/* 82371AB/EB/MB use the same device ID value. */
+#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index a2060cbed0..6792ec4eb8 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -43,6 +43,8 @@ int print_mchbar(struct pci_dev *nb)
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_82443LX:
+ case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
printf("This northbrigde does not have MCHBAR.\n");
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index 5dd651ba12..d479bfdc06 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -203,6 +203,50 @@ static const io_register_t ich0_pm_registers[] = {
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t i82371xx_pm_registers[] = {
+ { 0x00, 2, "PMSTS" },
+ { 0x02, 2, "PMEN" },
+ { 0x04, 2, "PMCNTRL" },
+ { 0x06, 2, "RESERVED" },
+ { 0x08, 1, "PMTMR" },
+ { 0x09, 1, "RESERVED" },
+ { 0x0A, 1, "RESERVED" },
+ { 0x0B, 1, "RESERVED" },
+ { 0x0C, 2, "GPSTS" },
+ { 0x0E, 2, "GPEN" },
+ { 0x10, 4, "PCNTRL" },
+#if DANGEROUS_REGISTERS
+ /*
+ * This register returns 0 on read, but reading it may cause
+ * the system to enter C2 state, which might hang the system.
+ */
+ { 0x14, 1, "PLVL2" },
+ { 0x15, 1, "PLVL3" },
+ { 0x16, 2, "RESERVED" },
+#endif
+ { 0x18, 2, "GLBSTS" },
+ { 0x1A, 2, "RESERVED" },
+ { 0x1c, 4, "DEVSTS" },
+ { 0x20, 2, "GLBEN" },
+ { 0x22, 1, "RESERVED" },
+ { 0x23, 1, "RESERVED" },
+ { 0x24, 1, "RESERVED" },
+ { 0x25, 1, "RESERVED" },
+ { 0x26, 1, "RESERVED" },
+ { 0x27, 1, "RESERVED" },
+ { 0x28, 4, "GLBCTL" },
+ { 0x2C, 4, "DEVCTL" },
+ /* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */
+ { 0x30, 1, "GPIREG 0" },
+ { 0x31, 1, "GPIREG 1" },
+ { 0x32, 1, "GPIREG 2" },
+ { 0x33, 1, "GPIREG 3" },
+ { 0x34, 1, "GPOREG 0" },
+ { 0x35, 1, "GPOREG 1" },
+ { 0x36, 1, "GPOREG 2" },
+ { 0x37, 1, "GPOREG 3" },
+};
+
int print_pmbase(struct pci_dev *sb)
{
int i, size;
@@ -230,6 +274,11 @@ int print_pmbase(struct pci_dev *sb)
pm_registers = ich0_pm_registers;
size = ARRAY_SIZE(ich0_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_82371XX:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = i82371xx_pm_registers;
+ size = ARRAY_SIZE(i82371xx_pm_registers);
+ break;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have PMBASE.\n");
return 1;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 06:57:34 +0000