diff options
Diffstat (limited to 'util')
| -rw-r--r-- | util/inteltool/cpu.c | 229 |
1 files changed, 229 insertions, 0 deletions
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 360b86b9d0..c40a3bd22b 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -868,6 +868,234 @@ int print_intel_core_msrs(void) }; + /* + * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual + * September 2016 + */ + static const msr_entry_t modelf6x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x002b, "MSR_EBC_SOFT_POWERON" }, + { 0x002c, "MSR_EBC_FREQUENCY_ID" }, +// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01a1, "MSR_PLATFORM_BRV" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + { 0x0302, "MSR_BPU_COUNTER2" }, + { 0x0303, "MSR_BPU_COUNTER3" }, + { 0x0304, "MSR_MS_COUNTER0" }, + { 0x0305, "MSR_MS_COUNTER1" }, + { 0x0306, "MSR_MS_COUNTER2" }, + { 0x0307, "MSR_MS_COUNTER3" }, + { 0x0308, "MSR_FLAME_COUNTER0" }, + { 0x0309, "MSR_FLAME_COUNTER1" }, + { 0x030a, "MSR_FLAME_COUNTER2" }, + { 0x030b, "MSR_FLAME_COUNTER3" }, + { 0x030c, "MSR_IQ_COUNTER0" }, + { 0x030d, "MSR_IQ_COUNTER1" }, + { 0x030e, "MSR_IQ_COUNTER2" }, + { 0x030f, "MSR_IQ_COUNTER3" }, + { 0x0310, "MSR_IQ_COUNTER4" }, + { 0x0311, "MSR_IQ_COUNTER5" }, + { 0x0360, "MSR_BPU_CCCR0" }, + { 0x0361, "MSR_BPU_CCCR1" }, + { 0x0362, "MSR_BPU_CCCR2" }, + { 0x0363, "MSR_BPU_CCCR3" }, + { 0x0364, "MSR_MS_CCCR0" }, + { 0x0365, "MSR_MS_CCCR1" }, + { 0x0366, "MSR_MS_CCCR2" }, + { 0x0367, "MSR_MS_CCCR3" }, + { 0x0368, "MSR_FLAME_CCCR0" }, + { 0x0369, "MSR_FLAME_CCCR1" }, + { 0x036A, "MSR_FLAME_CCCR2" }, + { 0x036B, "MSR_FLAME_CCCR3" }, + { 0x036C, "MSR_IQ_CCCR0" }, + { 0x036D, "MSR_IQ_CCCR1" }, + { 0x036E, "MSR_IQ_CCCR2" }, + { 0x036F, "MSR_IQ_CCCR3" }, + { 0x0370, "MSR_IQ_CCCR4" }, + { 0x0371, "MSR_IQ_CCCR5" }, + { 0x03A0, "MSR_BSU_ESCR0" }, + { 0x03A1, "MSR_BSU_ESCR1" }, + { 0x03A2, "MSR_FSB_ESCR0" }, + { 0x03A3, "MSR_FSB_ESCR1" }, + { 0x03A4, "MSR_FIRM_ESCR0" }, + { 0x03A5, "MSR_FIRM_ESCR1" }, + { 0x03A6, "MSR_FLAME_ESCR0" }, + { 0x03A7, "MSR_FLAME_ESCR1" }, + { 0x03A8, "MSR_DAC_ESCR0" }, + { 0x03A9, "MSR_DAC_ESCR1" }, + { 0x03AA, "MSR_MOB_ESCR0" }, + { 0x03AB, "MSR_MOB_ESCR1" }, + { 0x03AC, "MSR_PMH_ESCR0" }, + { 0x03AD, "MSR_PMH_ESCR1" }, + { 0x03AE, "MSR_SAAT_ESCR0" }, + { 0x03AF, "MSR_SAAT_ESCR1" }, + { 0x03B0, "MSR_U2L_ESCR0" }, + { 0x03B1, "MSR_U2L_ESCR1" }, + { 0x03B2, "MSR_BPU_ESCR0" }, + { 0x03B3, "MSR_BPU_ESCR1" }, + { 0x03B4, "MSR_IS_ESCR0" }, + { 0x03B5, "MSR_IS_ESCR1" }, + { 0x03B6, "MSR_ITLB_ESCR0" }, + { 0x03B7, "MSR_ITLB_ESCR1" }, + { 0x03B8, "MSR_CRU_ESCR0" }, + { 0x03B9, "MSR_CRU_ESCR1" }, + { 0x03BA, "MSR_IQ_ESCR0" }, + { 0x03BB, "MSR_IQ_ESCR1" }, + { 0x03BC, "MSR_RAT_ESCR0" }, + { 0x03BD, "MSR_RAT_ESCR1" }, + { 0x03BE, "MSR_SSU_ESCR0" }, + { 0x03C0, "MSR_MS_ESCR0" }, + { 0x03C1, "MSR_MS_ESCR1" }, + { 0x03C2, "MSR_TBPU_ESCR0" }, + { 0x03C3, "MSR_TBPU_ESCR1" }, + { 0x03C4, "MSR_TC_ESCR0" }, + { 0x03C5, "MSR_TC_ESCR1" }, + { 0x03C8, "MSR_IX_ESCR0" }, + { 0x03C9, "MSR_IX_ESCR1" }, + { 0x03CA, "MSR_ALF_ESCR0" }, + { 0x03CB, "MSR_ALF_ESCR1" }, + { 0x03CC, "MSR_CRU_ESCR2" }, + { 0x03CD, "MSR_CRU_ESCR3" }, + { 0x03E0, "MSR_CRU_ESCR4" }, + { 0x03E1, "MSR_CRU_ESCR5" }, + { 0x03F0, "MSR_TC_PRECISE_EVENT" }, + { 0x03F1, "MSR_PEBS_ENABLE" }, + { 0x03F2, "MSR_PEBS_MATRIX_VERT" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040b, "IA32_MC2_MISC" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x040f, "IA32_MC3_MISC" }, + }; + + static const msr_entry_t modelf6x_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0180, "MSR_MCG_RAX" }, + { 0x0181, "MSR_MCG_RBX" }, + { 0x0182, "MSR_MCG_RCX" }, + { 0x0183, "MSR_MCG_RDX" }, + { 0x0184, "MSR_MCG_RSI" }, + { 0x0185, "MSR_MCG_RDI" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x018a, "MSR_MCG_MISC" }, + { 0x0190, "MSR_MCG_R8" }, + { 0x0191, "MSR_MCG_R9" }, + { 0x0192, "MSR_MCG_R10" }, + { 0x0193, "MSR_MCG_R11" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0195, "MSR_MCG_R13" }, + { 0x0196, "MSR_MCG_R14" }, + { 0x0197, "MSR_MCG_R15" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01A2, "MSR_TEMPERATURE_TARGET" }, + { 0x01d7, "MSR_LER_FROM_LIP" }, + { 0x01d8, "MSR_LER_TO_LIP" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01da, "MSR_LASTBRANCH_TOS" }, + { 0x0277, "IA32_PAT" }, + { 0x0600, "IA32_DS_AREA" }, + { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, + { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, + { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, + { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, + { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, + { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, + { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, + { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, + { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, + { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, + { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, + { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, + { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, + { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, + { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, + { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, + { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, + /* Intel Xeon processor 7100 with L3 */ +// { 0x107CC, "MSR_EMON_L3_CTR_CTL0" }, +// { 0x107CD, "MSR_EMON_L3_CTR_CTL1" }, +// { 0x107CE, "MSR_EMON_L3_CTR_CTL2" }, +// { 0x107CF, "MSR_EMON_L3_CTR_CTL3" }, +// { 0x107D0, "MSR_EMON_L3_CTR_CTL4" }, +// { 0x107D1, "MSR_EMON_L3_CTR_CTL5" }, +// { 0x107D2, "MSR_EMON_L3_CTR_CTL6" }, +// { 0x107D3, "MSR_EMON_L3_CTR_CTL7" }, + }; + /* Atom N455 * * This should apply to the following processors: @@ -1316,6 +1544,7 @@ int print_intel_core_msrs(void) { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, + { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, |