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-rw-r--r--targets/intel/d945gclf/Config-abuild.lb46
-rw-r--r--targets/intel/d945gclf/Config.lb10
-rw-r--r--targets/intel/eagleheights/Config.lb32
-rw-r--r--targets/intel/mtarvon/Config.lb40
-rw-r--r--targets/intel/truxton/Config.lb40
-rw-r--r--targets/intel/xe7501devkit/Config.lb37
-rw-r--r--targets/intel/xe7501devkit/VERSION1
7 files changed, 0 insertions, 206 deletions
diff --git a/targets/intel/d945gclf/Config-abuild.lb b/targets/intel/d945gclf/Config-abuild.lb
deleted file mode 100644
index 5b6df72d87..0000000000
--- a/targets/intel/d945gclf/Config-abuild.lb
+++ /dev/null
@@ -1,46 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-option CONFIG_ROM_SIZE=512*1024
-
-romimage "normal"
- option CONFIG_USE_FALLBACK_IMAGE=0
- option COREBOOT_EXTRA_VERSION=".0-normal"
- payload __PAYLOAD__
-end
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=1
- option COREBOOT_EXTRA_VERSION=".0-fallback"
- payload __PAYLOAD__
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
-#pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772
-
diff --git a/targets/intel/d945gclf/Config.lb b/targets/intel/d945gclf/Config.lb
deleted file mode 100644
index 1c3057b8d2..0000000000
--- a/targets/intel/d945gclf/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-target d945gclf
-mainboard intel/d945gclf
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE = 1
- payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
-
diff --git a/targets/intel/eagleheights/Config.lb b/targets/intel/eagleheights/Config.lb
deleted file mode 100644
index b04c6a06e0..0000000000
--- a/targets/intel/eagleheights/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-target eagleheights
-mainboard intel/eagleheights
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 1024 * 1024
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=1
- payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/mtarvon/Config.lb b/targets/intel/mtarvon/Config.lb
deleted file mode 100644
index 87dc4f9d45..0000000000
--- a/targets/intel/mtarvon/Config.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-target mtarvon
-mainboard intel/mtarvon
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=1
- payload /tmp/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/truxton/Config.lb b/targets/intel/truxton/Config.lb
deleted file mode 100644
index fd6a7bd3ca..0000000000
--- a/targets/intel/truxton/Config.lb
+++ /dev/null
@@ -1,40 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-target truxton
-mainboard intel/truxton
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 2 * 1024 * 1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=1
- payload /tmp/seabios.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/xe7501devkit/Config.lb b/targets/intel/xe7501devkit/Config.lb
deleted file mode 100644
index 8e70031198..0000000000
--- a/targets/intel/xe7501devkit/Config.lb
+++ /dev/null
@@ -1,37 +0,0 @@
-target xe7501devkit
-mainboard intel/xe7501devkit
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-option CONFIG_ROM_SIZE = 192*1024
-
-## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE = 0x1B000
-
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
-## (including payload) will use
-option CONFIG_FALLBACK_SIZE = 0
-
-
-
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=0
-# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-# payload ../../../../../../../memtest86/memtest
-# payload ../../../../../../../etherboot/src/bin/e1000.zelf
- payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-# payload ../../../../../../../QNX/BSP/images/qnxbasesmp.elf
-end
-
-#NOTE: CMOS currently not supported due to conflicts with factory BIOS
-# Thus no support for fallback boot.
-#romimage "fallback"
-# option CONFIG_USE_FALLBACK_IMAGE=1
-# option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-# payload ../../../../../../../memtest86/memtest
-# payload ../../../../../../../etherboot/src/bin/e1000.zelf
-# payload ../../../../../../../etherboot/src/bin/e1000--filo.zelf
-#end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/intel/xe7501devkit/VERSION b/targets/intel/xe7501devkit/VERSION
deleted file mode 100644
index 49d59571fb..0000000000
--- a/targets/intel/xe7501devkit/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-0.1