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Diffstat (limited to 'targets/artecgroup/dbe61/Config.lb')
| -rw-r--r-- | targets/artecgroup/dbe61/Config.lb | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb deleted file mode 100644 index eaa979c6f5..0000000000 --- a/targets/artecgroup/dbe61/Config.lb +++ /dev/null @@ -1,32 +0,0 @@ -# Config file for the ThinCan dbe61 - -target dbe61 -mainboard artecgroup/dbe61 - -# HACK to get the right TSC support. -option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 -option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 - -## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use -## (normal AND fallback images and payloads). -## leave 36k for vsa and 32K for video ROM -#option CONFIG_ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024 - -#No VGA for now -option CONFIG_ROM_SIZE = 1024*512 - 36*1024 - -# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, -## not including any payload. -option CONFIG_ROM_IMAGE_SIZE=64*1024 - -option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -romimage "fallback" - option CONFIG_USE_FALLBACK_IMAGE=1 - option COREBOOT_EXTRA_VERSION=".0Fallback" - payload ../payload.elf -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" |