17 files changed, 3 insertions, 111 deletions

diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 5b9284220b..e3f9aec266 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -25,9 +25,6 @@ config HASWELL_VBOOT_IN_BOOTBLOCK
 	  binary is used meaning a jump is made from RW to the RO region
 	  and back to the RW region after the binary is done.
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index e06bdac4c1..215560f84b 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -32,9 +32,6 @@ config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
 	  binary is used meaning a jump is made from RW to the RO region
 	  and back to the RW region after the binary is done.
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 2057ad420e..bcf28d81bd 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -299,7 +299,6 @@ config ACPI_SSDT_PSD_INDEPENDENT
 	  choose to generate _PSD object to allow cores to transition together.
 
 config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
 	select ALWAYS_LOAD_OPROM
 	select ALWAYS_RUN_OPROM
 
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1c694544b0..916e5f38ee 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -213,9 +213,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0x7fff
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 62049b5abe..9fe2c29ea5 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -114,9 +114,6 @@ config MAX_CPUS
 	int
 	default 4
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index f539be88fe..8811b38cf9 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -37,9 +37,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_HAS_L2_ENABLE_MSR
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 720597c59a..0e1b6db34f 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -52,9 +52,6 @@ config DCACHE_BSP_STACK_SIZE
 	  The amount of anticipated stack usage in CAR by bootblock and
 	  other stages.
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index bf84f7a2db..7528c09fd3 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -73,9 +73,6 @@ config BROADWELL_VBOOT_IN_BOOTBLOCK
 	  binary is used meaning a jump is made from RW to the RO region
 	  and back to the RW region after the binary is done.
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 49ec1b1b6d..dd7d69942b 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -260,9 +260,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0xc35
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 25804d7d02..3b17a0ed88 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -171,9 +171,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0xc35
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 501e6c3339..f28209f581 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -164,9 +164,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0xc35
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 08bd4be651..72912f7a64 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -172,9 +172,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0xc35
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7401d5ef50..a7e25b126c 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -92,9 +92,6 @@ config CPU_INTEL_NUM_FIT_ENTRIES
 	int
 	default 10
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 3e080cce60..c6bb167c9f 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -191,9 +191,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
 	default 0x7fff
 
-config CHROMEOS
-	select CHROMEOS_RAMOOPS_DYNAMIC
-
 # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
 # in all low power states.  Cr50 TPM, if used, needs to be told to generate longer pulses.
 config TPM_CR50
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index d5254ac8cc..e81f31d196 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -29,21 +29,6 @@ config CHROMEOS_RAMOOPS
 	bool "Reserve space for Chrome OS ramoops"
 	default y
 
-config CHROMEOS_RAMOOPS_DYNAMIC
-	bool "Allocate RAM oops buffer in cbmem"
-	default n
-	depends on CHROMEOS_RAMOOPS && HAVE_ACPI_TABLES
-
-config CHROMEOS_RAMOOPS_NON_ACPI
-	bool "Allocate RAM oops buffer in cbmem passed through cb tables to payload"
-	default y if !HAVE_ACPI_TABLES
-	depends on CHROMEOS_RAMOOPS && !HAVE_ACPI_TABLES
-
-config CHROMEOS_RAMOOPS_RAM_START
-	hex "Physical address of preserved RAM"
-	default 0x00f00000
-	depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC
-
 config CHROMEOS_RAMOOPS_RAM_SIZE
 	hex "Size of preserved RAM"
 	default 0x00100000
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index d023075b3d..35e2dde740 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -27,10 +27,7 @@ static inline void reboot_from_watchdog(void) { return; }
  */
 void mainboard_prepare_cr50_reset(void);
 
-struct romstage_handoff;
-
 #include "gnvs.h"
-struct device;
 
 #if CONFIG(CHROMEOS_RAMOOPS)
 void chromeos_ram_oops_init(chromeos_acpi_t *chromeos);
@@ -38,8 +35,6 @@ void chromeos_ram_oops_init(chromeos_acpi_t *chromeos);
 static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {}
 #endif /* CONFIG_CHROMEOS_RAMOOPS */
 
-void chromeos_reserve_ram_oops(struct device *dev, int idx);
-
 void cbmem_add_vpd_calibration_data(void);
 void chromeos_set_me_hash(u32*, int);
 
@@ -66,6 +61,7 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num);
  */
 void mainboard_chromeos_acpi_generate(void);
 #if CONFIG(CHROMEOS)
+struct device;
 void chromeos_dsdt_generator(const struct device *dev);
 #else
 #define chromeos_dsdt_generator NULL
diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c
index 119912bd20..ae72133d11 100644
--- a/src/vendorcode/google/chromeos/ramoops.c
+++ b/src/vendorcode/google/chromeos/ramoops.c
@@ -24,66 +24,17 @@ static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size)
 	chromeos->ramoops_len = size;
 }
 
-static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos)
+void chromeos_ram_oops_init(chromeos_acpi_t *chromeos)
 {
 	const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE;
 	void *ram_oops;
 
-	if (!CONFIG(CHROMEOS_RAMOOPS_DYNAMIC))
-		return;
-
 	ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size);
 
 	set_ramoops(chromeos, ram_oops, size);
 }
 
-#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)
-static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {}
-#else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */
-
-static const unsigned long ramoops_base = CONFIG_CHROMEOS_RAMOOPS_RAM_START;
-static const unsigned long ramoops_size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE;
-
-/*
- * Save pointer to chromeos structure in memory. This is needed because the
- * memory reservation is not done when chromeos_init() is called. However,
- * the pointer to the chromeos_acpi_t structure is needed to update the
- * fields with the rserved base and size.
- */
-static chromeos_acpi_t *g_chromeos;
-
-static void set_global_chromeos_pointer(chromeos_acpi_t *chromeos)
-{
-	g_chromeos = chromeos;
-}
-
-static void update_gnvs(void *arg)
-{
-	chromeos_acpi_t **chromeos = arg;
-
-	set_ramoops(*chromeos, (void *)ramoops_base, ramoops_size);
-}
-
-static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &g_chromeos);
-
-void chromeos_reserve_ram_oops(struct device *dev, int idx)
-{
-	const unsigned long base = ramoops_base >> 10;
-	const unsigned long size = ramoops_size >> 10;
-
-	reserved_ram_resource(dev, idx, base, size);
-
-	boot_state_sched_on_exit(&bscb_ramoops, BS_WRITE_TABLES);
-}
-#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */
-
-void chromeos_ram_oops_init(chromeos_acpi_t *chromeos)
-{
-	set_global_chromeos_pointer(chromeos);
-	reserve_ram_oops_dynamic(chromeos);
-}
-
-#elif CONFIG(CHROMEOS_RAMOOPS_NON_ACPI)
+#else
 
 static void ramoops_alloc(void *arg)
 {