diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/tyan/s1846/Config.lb | 188 | ||||
| -rw-r--r-- | src/mainboard/tyan/s1846/Options.lb | 154 | ||||
| -rw-r--r-- | src/mainboard/tyan/s1846/auto.c | 52 | ||||
| -rw-r--r-- | src/mainboard/tyan/s1846/chip.h | 4 | ||||
| -rw-r--r-- | src/mainboard/tyan/s1846/failover.c | 32 |
5 files changed, 132 insertions, 298 deletions
diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb index 6ef00554d6..09fa980e54 100644 --- a/src/mainboard/tyan/s1846/Config.lb +++ b/src/mainboard/tyan/s1846/Config.lb @@ -1,173 +1,131 @@ ## -## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## This file is part of the LinuxBIOS project. ## -if USE_FALLBACK_IMAGE - default ROM_SECTION_SIZE = FALLBACK_SIZE - default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) -else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 -end - -## -## Compute the start location and size size of -## The linuxBIOS bootloader. -## -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) - -## -## Compute where this copy of linuxBIOS will start in the boot rom +## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. ## -## Compute a range of ROM that can cached to speed up linuxBIOS, -## execution speed. +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE=65536 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) - -## -## Set all of the defaults for an x86 architecture +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) arch i386 end - -## -## Build the objects we have code for in this directory. -## - driver mainboard.o - -#if HAVE_PIRQ_TABLE object irq_tables.o end -#object reset.o - -## -## Romcc output -## +if HAVE_PIRQ_TABLE + object irq_tables.o +end makerule ./failover.E - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end - makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ./romcc" - action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end - -makerule ./auto.E - depends "$(MAINBOARD)/auto.c ./romcc" - action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end -makerule ./auto.inc +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" depends "$(MAINBOARD)/auto.c ./romcc" - action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end - -## -## Build our 16 bit and 32 bit linuxBIOS entry code -## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where linuxBIOS is entered) -## -if USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds end - -### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of linuxBIOS startup -### Things are delicate and we test to see if we should -### failover to another image. -### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit ./auto.inc mainboardinit cpu/x86/mmx/disable_mmx.inc -## -## Include the secondary Configuration files -## dir /pc80 config chip.h chip northbridge/intel/i440bx # Northbridge - device pci_domain 0 on + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - device pci 1.0 on end # AGP bridge + device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge chip superio/nsc/pc87309 # Super I/O - device pnp 2e.5 on # PS/2 keyboard (+ mouse?) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - # irq 0x72 = 12 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.b on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.c on # Com2 / IR + device pnp 2e.2 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.d on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.e on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + device pnp 2e.4 on # Power management end - device pnp 2e.f on # PS/2 mouse + device pnp 2e.5 on # PS/2 mouse irq 0x70 = 12 end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end end end - device pci 7.1 on end # IDE - device pci 7.2 on end # USB + device pci 7.1 on end # IDE + device pci 7.2 on end # USB device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" end end - chip cpu/intel/slot_2 # CPU - end end - diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb index 1ce855231e..ebec984879 100644 --- a/src/mainboard/tyan/s1846/Options.lb +++ b/src/mainboard/tyan/s1846/Options.lb @@ -1,3 +1,24 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -26,6 +47,7 @@ uses _ROMBASE uses _RAMBASE uses XIP_ROM_SIZE uses XIP_ROM_BASE +uses HAVE_MP_TABLE uses CROSS_COMPILE uses CC uses HOSTCC @@ -37,113 +59,41 @@ uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC - -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from linuxBIOS -## -default HAVE_HARD_RESET=0 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=0 -default IRQ_SLOT_COUNT=4 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=0 - -### -### LinuxBIOS layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default ROM_IMAGE_SIZE = 64 * 1024 default FALLBACK_SIZE = 128 * 1024 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 - default _RAMBASE = 0x00004000 - default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CROSS_COMPILE="" -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the linuxBIOS loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=9 - -default CONFIG_UDELAY_TSC=1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 end - diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c index 7bb2a41788..fdb8f7550b 100644 --- a/src/mainboard/tyan/s1846/auto.c +++ b/src/mainboard/tyan/s1846/auto.c @@ -31,12 +31,12 @@ #include "ram/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" -#include "mainboard/bitworks/ims/debug.c" // FIXME +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "superio/nsc/pc87309/pc87309_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include "superio/nsc/pc87309/pc87309_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) @@ -49,64 +49,24 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/intel/i440bx/debug.c" #include "sdram/generic_sdram.c" -static void enable_mainboard_devices(void) -{ - device_t dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); - - if (dev == PCI_DEV_INVALID) { - die("Southbridge not found!\n"); - } else { - print_debug("Southbridge found!\n"); - } -} - static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 0), .channel0 = {0x50, 0x51, 0x52, 0x53}, - }, + } }; - /* Skip this if there was a built in self test failure. */ - if (bist == 0) { + if (bist == 0) early_mtrr_init(); - } pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - - enable_mainboard_devices(); - enable_smbus(); - - dump_spd_registers(&memctrl[0]); - + /* dump_spd_registers(&memctrl[0]); */ sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - - /* Check whether RAM is working. - * - * Do _not_ check the area from 640 KB - 768 KB, as that's not really - * RAM, but rather reserved for the 'Video Buffer Area'. - * - * Other stuff in the range from 640 KB - 1 MB: - * - * - 640 KB - 768 KB: Video Buffer Area - * - 768 KB - 896 KB: Expansion Area - * - 896 KB - 960 KB: Extended System BIOS Area - * - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area - * - * Trying to check these areas will usually fail, too. However, you - * probably can set the PAM registers of the northbridge to map - * those areas to RAM (read/write). In that case you can use the - * range from 768 KB - 1 MB as normal RAM, and thus check it here. - */ - ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ - ram_check(0x000c0000, 0x00100000); /* 768 KB - 1 MB */ - // ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ + /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/tyan/s1846/chip.h b/src/mainboard/tyan/s1846/chip.h index f82ae70333..f53f5dbede 100644 --- a/src/mainboard/tyan/s1846/chip.h +++ b/src/mainboard/tyan/s1846/chip.h @@ -19,6 +19,4 @@ */ extern struct chip_operations mainboard_tyan_s1846_ops; - -struct mainboard_tyan_s1846_config { -}; +struct mainboard_tyan_s1846_config {}; diff --git a/src/mainboard/tyan/s1846/failover.c b/src/mainboard/tyan/s1846/failover.c index bdcb9eaed2..e69de29bb2 100644 --- a/src/mainboard/tyan/s1846/failover.c +++ b/src/mainboard/tyan/s1846/failover.c @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} |