diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 12 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 5 |
2 files changed, 15 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2b18b3b4b4..0399dc1709 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -25,6 +25,7 @@ chip soc/intel/cannonlake #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | + #| GSPI1 | FP MCU | #| I2C0 | Touchpad | #| I2C1 | Touch screen | #| I2C4 | Audio | @@ -321,7 +322,16 @@ chip soc/intel/cannonlake device spi 0 on end end end # GSPI #0 - device pci 1e.3 off end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 93e0af1753..73d6645c71 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -62,7 +62,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT), /* A22 : FPMCU_PCH_BOOT0 */ PAD_CFG_GPO(GPP_A22, 0, DEEP), - /* A23 : FPMCU_PCH_INT_ODL */ + /* A23 : FPMCU_PCH_INT_ODL + * TODO Configure it back to invert mode, when + * ITSS IPCx configuration is fixed in FSP. + */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE), /* B0 : CORE_VID0 */ |