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-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c16
-rw-r--r--src/northbridge/amd/agesa/family15tn/iommu.c4
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c34
-rw-r--r--src/northbridge/amd/agesa/family16kb/northbridge.c66
4 files changed, 60 insertions, 60 deletions
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index df52bf94f7..d26695cd5d 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -38,13 +38,13 @@
#define FX_DEVS 1
-static device_t __f0_dev[FX_DEVS];
-static device_t __f1_dev[FX_DEVS];
-static device_t __f2_dev[FX_DEVS];
-static device_t __f4_dev[FX_DEVS];
+static struct device *__f0_dev[FX_DEVS];
+static struct device *__f1_dev[FX_DEVS];
+static struct device *__f2_dev[FX_DEVS];
+static struct device *__f4_dev[FX_DEVS];
static unsigned fx_devs = 0;
-static device_t get_node_pci(u32 nodeid, u32 fn)
+static struct device *get_node_pci(u32 nodeid, u32 fn)
{
if ((CONFIG_CDB + nodeid) < 32) {
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
@@ -355,7 +355,7 @@ static void set_resource(struct device *dev, struct resource *resource,
}
#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)
-extern device_t vga_pri; // the primary vga device, defined in device.c
+extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
static void create_vga_resource(struct device *dev, unsigned nodeid)
@@ -618,7 +618,7 @@ static void cpu_bus_init(struct device *dev)
/* North Bridge Structures */
-static void northbridge_fill_ssdt_generator(device_t device)
+static void northbridge_fill_ssdt_generator(struct device *device)
{
msr_t msr;
char pscope[] = "\\_SB.PCI0";
@@ -659,7 +659,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
return (unsigned long)current;
}
-static unsigned long agesa_write_acpi_tables(device_t device,
+static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
{
diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c
index 4b9eda06e3..d6dc7dac67 100644
--- a/src/northbridge/amd/agesa/family15tn/iommu.c
+++ b/src/northbridge/amd/agesa/family15tn/iommu.c
@@ -19,7 +19,7 @@
#include <device/pci_ops.h>
#include <lib.h>
-static void iommu_read_resources(device_t dev)
+static void iommu_read_resources(struct device *dev)
{
struct resource *res;
@@ -35,7 +35,7 @@ static void iommu_read_resources(device_t dev)
res->flags = IORESOURCE_MEM;
}
-static void iommu_set_resources(device_t dev)
+static void iommu_set_resources(struct device *dev)
{
struct resource *res;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index f47d312291..21badfe622 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -49,15 +49,15 @@ typedef struct dram_base_mask {
static unsigned node_nums;
static unsigned sblink;
-static device_t __f0_dev[MAX_NODE_NUMS];
-static device_t __f1_dev[MAX_NODE_NUMS];
-static device_t __f2_dev[MAX_NODE_NUMS];
-static device_t __f4_dev[MAX_NODE_NUMS];
+static struct device *__f0_dev[MAX_NODE_NUMS];
+static struct device *__f1_dev[MAX_NODE_NUMS];
+static struct device *__f2_dev[MAX_NODE_NUMS];
+static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
- device_t dev;
+ struct device *dev;
dram_base_mask_t d;
dev = __f1_dev[0];
u32 temp;
@@ -73,7 +73,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
return d;
}
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 i;
@@ -100,7 +100,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
pci_write_config32(__f1_dev[i], reg, tempreg);
}
-static device_t get_node_pci(u32 nodeid, u32 fn)
+static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
@@ -143,7 +143,7 @@ static void f1_write_config32(unsigned reg, u32 value)
if (fx_devs == 0)
get_fx_devs();
for (i = 0; i < fx_devs; i++) {
- device_t dev;
+ struct device *dev;
dev = __f1_dev[i];
if (dev && dev->enabled) {
pci_write_config32(dev, reg, value);
@@ -451,7 +451,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
return (unsigned long)current;
}
-static void northbridge_fill_ssdt_generator(device_t device)
+static void northbridge_fill_ssdt_generator(struct device *device)
{
msr_t msr;
char pscope[] = "\\_SB.PCI0";
@@ -472,7 +472,7 @@ static void northbridge_fill_ssdt_generator(device_t device)
acpigen_pop_len();
}
-static unsigned long agesa_write_acpi_tables(device_t device,
+static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
{
@@ -604,7 +604,7 @@ static void domain_read_resources(struct device *dev)
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
- device_t reg_dev;
+ struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
@@ -786,7 +786,7 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus,
};
-static void sysconf_init(device_t dev) // first node
+static void sysconf_init(struct device *dev) // first node
{
sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
@@ -828,12 +828,12 @@ static void add_more_links(struct device *dev, unsigned total_links)
last->next = NULL;
}
-static void cpu_bus_scan(device_t dev)
+static void cpu_bus_scan(struct device *dev)
{
struct bus *cpu_bus;
- device_t dev_mc;
+ struct device *dev_mc;
#if CONFIG_CBB
- device_t pci_domain;
+ struct device *pci_domain;
#endif
int i,j;
int coreid_bits;
@@ -913,7 +913,7 @@ static void cpu_bus_scan(device_t dev)
/* Find which cpus are present */
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
- device_t cdb_dev;
+ struct device *cdb_dev;
unsigned busn, devn;
struct bus *pbus;
@@ -997,7 +997,7 @@ static void cpu_bus_scan(device_t dev)
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
+ struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 8e5e4725d8..760d1a1680 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -48,15 +48,15 @@ typedef struct dram_base_mask {
static unsigned node_nums;
static unsigned sblink;
-static device_t __f0_dev[MAX_NODE_NUMS];
-static device_t __f1_dev[MAX_NODE_NUMS];
-static device_t __f2_dev[MAX_NODE_NUMS];
-static device_t __f4_dev[MAX_NODE_NUMS];
+static struct device *__f0_dev[MAX_NODE_NUMS];
+static struct device *__f1_dev[MAX_NODE_NUMS];
+static struct device *__f2_dev[MAX_NODE_NUMS];
+static struct device *__f4_dev[MAX_NODE_NUMS];
static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
- device_t dev;
+ struct device *dev;
dram_base_mask_t d;
dev = __f1_dev[0];
u32 temp;
@@ -72,7 +72,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
return d;
}
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 i;
@@ -99,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
pci_write_config32(__f1_dev[i], reg, tempreg);
}
-static device_t get_node_pci(u32 nodeid, u32 fn)
+static struct device *get_node_pci(u32 nodeid, u32 fn)
{
#if MAX_NODE_NUMS + CONFIG_CDB >= 32
if ((CONFIG_CDB + nodeid) < 32) {
@@ -142,7 +142,7 @@ static void f1_write_config32(unsigned reg, u32 value)
if (fx_devs == 0)
get_fx_devs();
for (i = 0; i < fx_devs; i++) {
- device_t dev;
+ struct device *dev;
dev = __f1_dev[i];
if (dev && dev->enabled) {
pci_write_config32(dev, reg, value);
@@ -150,7 +150,7 @@ static void f1_write_config32(unsigned reg, u32 value)
}
}
-static u32 amdfam16_nodeid(device_t dev)
+static u32 amdfam16_nodeid(struct device *dev)
{
#if MAX_NODE_NUMS == 64
unsigned busn;
@@ -185,7 +185,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
* @retval 0 resource exists, not usable
* @retval 1 resource exist, resource has been allocated before
*/
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+static int reg_useable(unsigned reg, struct device *goal_dev, unsigned goal_nodeid,
unsigned goal_link)
{
struct resource *res;
@@ -193,7 +193,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
int result;
res = 0;
for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
- device_t dev;
+ struct device *dev;
dev = __f0_dev[nodeid];
if (!dev)
continue;
@@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
return result;
}
-static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+static struct resource *amdfam16_find_iopair(struct device *dev, unsigned nodeid, unsigned link)
{
struct resource *resource;
u32 free_reg, reg;
@@ -240,7 +240,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi
return resource;
}
-static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link)
+static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link)
{
struct resource *resource;
u32 free_reg, reg;
@@ -266,7 +266,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link
return resource;
}
-static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
+static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link)
{
struct resource *resource;
@@ -308,7 +308,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void read_resources(device_t dev)
+static void read_resources(struct device *dev)
{
u32 nodeid;
struct bus *link;
@@ -328,7 +328,7 @@ static void read_resources(device_t dev)
mmconf_resource(dev, 0xc0010058);
}
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
+static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
{
resource_t rbase, rend;
unsigned reg, link_num;
@@ -379,7 +379,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
* but it is too difficult to deal with the resource allocation magic.
*/
-static void create_vga_resource(device_t dev, unsigned nodeid)
+static void create_vga_resource(struct device *dev, unsigned nodeid)
{
struct bus *link;
@@ -388,7 +388,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)
- extern device_t vga_pri; // the primary vga device, defined in device.c
+ extern struct device *vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
@@ -407,7 +407,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
set_vga_enable_reg(nodeid, sblink);
}
-static void set_resources(device_t dev)
+static void set_resources(struct device *dev)
{
unsigned nodeid;
struct bus *bus;
@@ -451,7 +451,7 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
return (unsigned long)current;
}
-static void northbridge_fill_ssdt_generator(device_t device)
+static void northbridge_fill_ssdt_generator(struct device *device)
{
msr_t msr;
char pscope[] = "\\_SB.PCI0";
@@ -472,7 +472,7 @@ static void northbridge_fill_ssdt_generator(device_t device)
acpigen_pop_len();
}
-static unsigned long agesa_write_acpi_tables(device_t device,
+static unsigned long agesa_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
{
@@ -587,7 +587,7 @@ static const struct pci_driver family10_northbridge __pci_driver = {
static void fam16_finalize(void *chip_info)
{
- device_t dev;
+ struct device *dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
@@ -606,7 +606,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = {
.final = fam16_finalize,
};
-static void domain_read_resources(device_t dev)
+static void domain_read_resources(struct device *dev)
{
unsigned reg;
@@ -619,7 +619,7 @@ static void domain_read_resources(device_t dev)
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, reg_link;
- device_t reg_dev;
+ struct device *reg_dev;
if (reg < 0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30);
} else { // io
@@ -692,7 +692,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-static void domain_set_resources(device_t dev)
+static void domain_set_resources(struct device *dev)
{
unsigned long mmio_basek;
u32 pci_tolm;
@@ -811,13 +811,13 @@ static struct device_operations pci_domain_ops = {
.acpi_name = domain_acpi_name,
};
-static void sysconf_init(device_t dev) // first node
+static void sysconf_init(struct device *dev) // first node
{
sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
}
-static void add_more_links(device_t dev, unsigned total_links)
+static void add_more_links(struct device *dev, unsigned total_links)
{
struct bus *link, *last = NULL;
int link_num;
@@ -853,12 +853,12 @@ static void add_more_links(device_t dev, unsigned total_links)
last->next = NULL;
}
-static void cpu_bus_scan(device_t dev)
+static void cpu_bus_scan(struct device *dev)
{
struct bus *cpu_bus;
- device_t dev_mc;
+ struct device *dev_mc;
#if CONFIG_CBB
- device_t pci_domain;
+ struct device *pci_domain;
#endif
int i,j;
int coreid_bits;
@@ -938,7 +938,7 @@ static void cpu_bus_scan(device_t dev)
/* Find which cpus are present */
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
- device_t cdb_dev;
+ struct device *cdb_dev;
unsigned busn, devn;
struct bus *pbus;
@@ -1022,14 +1022,14 @@ static void cpu_bus_scan(device_t dev)
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
+ struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
}
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 22:19:56 +0000