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-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex231
-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex231
-rw-r--r--src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex231
-rw-r--r--src/mainboard/bap/ode_e21XX/BiosCallOuts.c34
-rw-r--r--src/mainboard/bap/ode_e21XX/Kconfig23
-rw-r--r--src/mainboard/bap/ode_e21XX/Makefile.inc20
-rw-r--r--src/mainboard/bap/ode_e21XX/OemCustomize.c28
-rw-r--r--src/mainboard/bap/ode_e21XX/acpi/superio.asl48
-rw-r--r--src/mainboard/bap/ode_e21XX/board_info.txt4
-rw-r--r--src/mainboard/bap/ode_e21XX/devicetree.cb80
-rw-r--r--src/mainboard/bap/ode_e21XX/dsdt.asl2
-rw-r--r--src/mainboard/bap/ode_e21XX/romstage.c16
12 files changed, 894 insertions, 54 deletions
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
new file mode 100644
index 0000000000..507c9f1174
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
@@ -0,0 +1,231 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+
+# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
+# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# Memory setting for DDR-1066
+
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x12 = Revision 1.2
+12
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+02
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 1 = 1 bit (bus width extension ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1/1 = 1ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns - used for DDR3
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock)
+0F
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 8 - 5 are supported
+1E 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x69 = 13.125ns - DDR3-1066F
+69
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x69 = 13.125ns - DDR3-1066F
+69
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x3C = 7.5ns
+3C
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x69 = 13.125ns - DDR3-1066F
+69
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x12C = 37.5ns - DDR3-1066 (see byte 21)
+2C
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x195 = 50.625ns - DDR3-1066F (see byte 21)
+95
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+80 07
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x0190 = 50ns - DDR3-1066, 2 KB page size
+01 90
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 0 = DLL Off mode supported
+03
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 0 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+04
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 - 59 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 116 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x80AD = Hynix
+80 AD
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x00 = 2000
+00 00
+
+# 121 Module ID: Module Manufacture week
+# 0x00 = 0th week
+00
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+E9 40
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
new file mode 100644
index 0000000000..1991f84fb2
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
@@ -0,0 +1,231 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+
+# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
+# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# Memory setting for DDR-1333
+
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x13 = Revision 1.3
+13
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+02
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 1 = 1 bit (bus width extension ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1/1 = 1ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns - used for DDR3
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x0C = tCKmin of 1.5 ns = DDR3-1333 (667 MHz clock)
+0C
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# Cas Latencies of 9 - 5 are supported (no 7)
+36 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x6C = 13.5ns - DDR3-1333H
+6C
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6C = 13.5ns - DDR3-1333H
+6C
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x3C = 7.5ns
+3C
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6C = 13.5ns - DDR3-1333H
+6C
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x120 = 36ns - DDR3-1333 (see byte 21)
+20
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x18C = 49.5ns - DDR3-1333H (see byte 21)
+8C
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x500 = 160ns - for 2 Gigabit chips
+80 07
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x0168 = 45ns - DDR3-1333, 2 KB page size
+01 68
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 0 = DLL Off mode supported
+03
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 0 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+04
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 - 59 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 116 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x80AD = Hynix
+80 AD
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x00 = 2000
+00 00
+
+# 121 Module ID: Module Manufacture week
+# 0x00 = 0th week
+00
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+95 b9
diff --git a/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
new file mode 100644
index 0000000000..e657179405
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
@@ -0,0 +1,231 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+
+# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
+# BAP ODE E21XX has 2GB ram soldered down on the Q7
+# Memory setting for DDR-800
+
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x11 = Revision 1.1
+11
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+02
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 1 = 1 bit (bus width extension ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1/1 = 1ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns - used for DDR3
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock)
+14
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# CAS Latencies of 6 - 5 are supported
+06 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x78 = 15ns - DDR3-800E
+78
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 15ns - DDR3-800E
+78
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x3C = 7.5ns
+3C
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6E = 15ns - DDR3-800E
+78
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x12C = 37.5ns - DDR3-800E (see byte 21)
+2C
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x1A4 = 52.5ns - DDR3-800E (see byte 21)
+A4
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x780 = 208ns - for 4 Gigabit chips
+80 07
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x0190 = 50ns - DDR3-800, 2 KB page size
+01 90
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 0 = DLL Off mode supported
+03
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 0 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+04
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 - 59 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 116 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x80AD = Hynix
+80 AD
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x00 = 2000
+00 00
+
+# 121 Module ID: Module Manufacture week
+# 0x00 = 0th week
+00
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+48 91
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 9528f72585..1b37865d17 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -25,15 +25,17 @@
#endif
#include "hudson.h"
#include <stdlib.h>
+#include <spd_cache.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
- {AGESA_READ_SPD, agesa_ReadSpd },
+ {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
@@ -303,3 +305,33 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
return AGESA_SUCCESS;
}
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ u8 index;
+
+ if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1066))
+ index = 1;
+ else if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1333))
+ index = 2;
+ else /* CONFIG_BAP_E21_DDR3_800 */
+ index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
+ if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig
index 426a99490d..b35674987c 100644
--- a/src/mainboard/bap/ode_e21XX/Kconfig
+++ b/src/mainboard/bap/ode_e21XX/Kconfig
@@ -26,6 +26,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_8192
select GFXUMA
+ select SUPERIO_FINTEK_F81866D
+ select SPD_CACHE
config MAINBOARD_DIR
string
@@ -51,4 +53,25 @@ config HUDSON_LEGACY_FREE
bool
default y
+choice
+ prompt "Select DDR3 clock"
+ default BAP_E21_DDR3_1333
+ help
+ Select your preferenced DDR3 clock setting.
+
+ Note: This option changes the total power consumption.
+
+ If unsure, use DDR3-1333.
+
+config BAP_E21_DDR3_800
+ bool "Select DDR3-800"
+
+config BAP_E21_DDR3_1066
+ bool "Select DDR3-1066"
+
+config BAP_E21_DDR3_1333
+ bool "Select DDR3-1333"
+
+endchoice
+
endif # BOARD_ODE_E21XX
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index 37c1dceead..4f4a11d7ce 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -18,3 +18,23 @@ romstage-y += OemCustomize.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066 BAP_Q7_1333
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c
index ac60c42082..3750ba4305 100644
--- a/src/mainboard/bap/ode_e21XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c
@@ -18,20 +18,10 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {
- /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
+ /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
- PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
- HotplugDisabled,
- PcieGenMaxSupported,
- PcieGenMaxSupported,
- AspmDisabled, 0x01, 0)
- },
- /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3),
PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
HotplugDisabled,
PcieGenMaxSupported,
@@ -71,23 +61,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
};
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
- /* DP0 to HDMI0/DP */
+ /* eDP0 to LVDS connector */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
},
- /* DP1 to FCH */
- {
- 0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
- },
- /* DP2 to HDMI1/DP */
+ /* DP1 to HDMI */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
},
};
diff --git a/src/mainboard/bap/ode_e21XX/acpi/superio.asl b/src/mainboard/bap/ode_e21XX/acpi/superio.asl
new file mode 100644
index 0000000000..92bd10680b
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/acpi/superio.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+ * (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* SuperIO support for Windows */
+
+Device (UAR1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ })
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ })
+}
+
+Device (UAR2) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 2)
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+ IRQNoFlags () {3}
+ })
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+ IRQNoFlags () {3}
+ })
+}
diff --git a/src/mainboard/bap/ode_e21XX/board_info.txt b/src/mainboard/bap/ode_e21XX/board_info.txt
index d2c6670225..dffb350694 100644
--- a/src/mainboard/bap/ode_e21XX/board_info.txt
+++ b/src/mainboard/bap/ode_e21XX/board_info.txt
@@ -1,5 +1,5 @@
-Board name: DB-FT3b (Olive Hill+)
-Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm
+Board name: ODE_e21xx
+Board URL: http://www.unibap.com/advanced-heterogeneous-computing-modules/
Category: eval
ROM protocol: SPI
ROM socketed: n
diff --git a/src/mainboard/bap/ode_e21XX/devicetree.cb b/src/mainboard/bap/ode_e21XX/devicetree.cb
index ee0cd98bfe..1a900c0c7c 100644
--- a/src/mainboard/bap/ode_e21XX/devicetree.cb
+++ b/src/mainboard/bap/ode_e21XX/devicetree.cb
@@ -30,10 +30,9 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
device pci 2.1 on end # x4 PCIe slot
- device pci 2.2 on end # mPCIe slot
- device pci 2.3 on end # Realtek NIC
- device pci 2.4 on end # Edge Connector
- device pci 2.5 on end # Edge Connector
+ device pci 2.2 on end # PCIe Q7 Realtek GBit LAN
+ device pci 2.3 on end # PCIe CB Realtek GBit LAN
+ device pci 2.4 on end # PCIe x2 BAP FPGA
device pci 8.0 on end # Platform Security Processor
end #chip northbridge/amd/pi/00730F01
@@ -42,18 +41,67 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 11.0 on end # SATA
device pci 12.0 on end # EHCI #0
device pci 13.0 on end # EHCI #1
- device pci 14.0 on # SMBus
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- end # SMbus
+ device pci 14.0 on end # SMBus
device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on end # LPC 0x439d
+ device pci 14.3 on # LPC 0x439d
+ chip superio/fintek/f81866d
+ register "hwm_amd_tsi_addr" = "0x98" # Set to AMD
+ register "hwm_amd_tsi_control" = "0x02" # Set to AMD
+ register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM
+ register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode
+ register "hwm_fan3_control" = "0x00" # Fan control 23kHz
+ register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz
+ register "hwm_fan2_bound1" = "0x3C" # 60°C
+ register "hwm_fan2_bound2" = "0x32" # 50°C
+ register "hwm_fan2_bound3" = "0x28" # 40°C
+ register "hwm_fan2_bound4" = "0x1E" # 30°C
+ register "hwm_fan2_seg1_speed" = "0xFF" # 100%
+ register "hwm_fan2_seg2_speed" = "0xD9" # 85%
+ register "hwm_fan2_seg3_speed" = "0xB2" # 70%
+ register "hwm_fan2_seg4_speed" = "0x99" # 60%
+ register "hwm_fan2_seg5_speed" = "0x80" # 50%
+ register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor
+ device pnp 4e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.3 off end # Parallel Port
+ device pnp 4e.4 on # Hardware Monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 4e.5 off # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 4e.6 off end # GPIO
+ device pnp 4e.7 on end # WDT
+ device pnp 4e.a off end # PME
+ device pnp 4e.10 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.11 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.12 off # COM3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 4e.13 off # COM4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 4e.14 off # COM5
+ end
+ device pnp 4e.15 off # COM6
+ end
+ end # f81866d
+ end #LPC
device pci 14.7 on end # SD
- device pci 16.0 on end # EHCI #2
end #chip southbridge/amd/pi/hudson
device pci 18.0 on end
@@ -62,10 +110,6 @@ chip northbridge/amd/pi/00730F01/root_complex
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
- register "spdAddrLookup" = "
- {
- { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses
- }"
end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex
end #domain
diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl
index 45ae428d9f..3afae7a8a6 100644
--- a/src/mainboard/bap/ode_e21XX/dsdt.asl
+++ b/src/mainboard/bap/ode_e21XX/dsdt.asl
@@ -69,6 +69,8 @@ DefinitionBlock (
/* Describe PCI INT[A-H] for the Southbridge */
#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+ /* Add UART support for Windows */
+ #include "acpi/superio.asl"
} /* End \_SB scope */
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index a5c529e7c5..8466e251db 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -32,6 +32,10 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f81866d/f81866d.h>
+
+#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -54,7 +58,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
-
+ fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
post_code(0x31);
console_init();
}
@@ -68,16 +72,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
- /*
- * This refers to LpcClkDrvSth settling time. Without this setting, processor
- * initialization is slow or incorrect, so this wait has been replicated from
- * earlier development boards.
- */
- {
- int i;
- for(i = 0; i < 200000; i++) inb(0xCD6);
- }
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 23:48:46 +0000