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-rw-r--r--src/mainboard/google/brya/variants/baseboard/brya/gpio.c84
1 files changed, 42 insertions, 42 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index 0583930b6c..88dbe0e05c 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -35,7 +35,7 @@ static const struct pad_config gpio_table[] = {
/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* A16 : USB_OC3# ==> USB_A0_OC_ODL */
- PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG),
/* A17 : DISP_MISCC ==> EN_FCAM_PWR */
PAD_CFG_GPO(GPP_A17, 1, DEEP),
/* A18 : DDSP_HPDB ==> HDMI_HPD */
@@ -56,19 +56,19 @@ static const struct pad_config gpio_table[] = {
/* B1 : SOC_VID1 */
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> M2_SSD_PLA_L */
- PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+ PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG),
/* B3 : PROC_GP2 ==> SAR2_INT_L */
- PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),
+ PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
- PAD_CFG_GPO(GPP_B4, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */
- PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
/* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
- PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
- PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
- PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* B9 : NC */
PAD_NC(GPP_B9, NONE),
/* B10 : NC */
@@ -82,11 +82,11 @@ static const struct pad_config gpio_table[] = {
/* B14 : SPKR ==> GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
/* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */
- PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
+ PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
- PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
/* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+ PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
PAD_NC(GPP_B18, NONE),
/* B19 : NC */
@@ -120,11 +120,11 @@ static const struct pad_config gpio_table[] = {
/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
PAD_NC(GPP_D0, NONE),
/* D1 : ISH_GP1 ==> FP_RST_ODL */
- PAD_CFG_GPO(GPP_D1, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
- PAD_CFG_GPO(GPP_D2, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> WCAM_RST_L */
- PAD_CFG_GPO(GPP_D3, 0, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_D4, 1, DEEP),
/* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */
@@ -136,33 +136,33 @@ static const struct pad_config gpio_table[] = {
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
/* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */
- PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG),
/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
- PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
- PAD_CFG_GPO(GPP_D11, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
PAD_NC(GPP_D12, NONE),
/* D13 : ISH_UART0_RXD ==> CAM_PSW_L */
- PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, EDGE_BOTH),
+ PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> SPKR_INT_L */
- PAD_CFG_GPI(GPP_D14, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */
- PAD_CFG_GPO(GPP_D15, 0, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
- PAD_CFG_GPO(GPP_D16, 0, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
/* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
- PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* D18 : UART1_TXD ==> SD_PE_RST_L */
- PAD_CFG_GPO(GPP_D18, 1, DEEP),
+ PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* E0 : see end of E group */
/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */
- PAD_CFG_GPI(GPP_E1, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
- PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> HPS_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE),
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
@@ -176,15 +176,15 @@ static const struct pad_config gpio_table[] = {
/* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */
PAD_CFG_GPO(GPP_E8, 1, DEEP),
/* E9 : USB_OC0# ==> USB_C0_OC_ODL */
- PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
/* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */
- PAD_CFG_GPI(GPP_E10, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */
- PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */
- PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
- PAD_CFG_GPI(GPP_E13, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : RSVD_TP ==> PCH_WP_OD */
@@ -192,7 +192,7 @@ static const struct pad_config gpio_table[] = {
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */
- PAD_CFG_GPI(GPP_E17, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
@@ -234,21 +234,21 @@ static const struct pad_config gpio_table[] = {
/* F10 : GPPF10_STRAP */
PAD_NC(GPP_F10, DN_20K),
/* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */
- PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
/* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */
- PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
- PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
- PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F15 : GSXSRESET# ==> FPMCU_INT_L */
- PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT),
+ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
- PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+ PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
- PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT),
+ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
- PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */
PAD_CFG_GPO(GPP_F19, 1, PLTRST),
/* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */
@@ -267,7 +267,7 @@ static const struct pad_config gpio_table[] = {
/* H2 : GPPH2_BOOT_STRAP3 */
PAD_NC(GPP_H2, NONE),
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
- PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+ PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG),
/* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */
@@ -387,7 +387,7 @@ static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
@@ -413,7 +413,7 @@ static const struct pad_config early_gpio_table[] = {
*/
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 21:16:01 +0000