diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 2 | ||||
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 6 | ||||
| -rw-r--r-- | src/drivers/usb/Kconfig | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/README | 2 | ||||
| -rw-r--r-- | src/mainboard/via/epia-m700/romstage.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i82810/raminit.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 |
13 files changed, 16 insertions, 16 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 53056038b7..3f0eca5f95 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -378,7 +378,7 @@ fam15_skip_dram_mtrr_setup: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 442c2b4a33..ac17571783 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -233,7 +233,7 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index d8a4fd9a83..db779fae7e 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -306,7 +306,7 @@ no_msr_11e: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index f0d49390ba..388c2ea23c 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -132,7 +132,7 @@ clear_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 93d690748f..33a7a6c57e 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -138,7 +138,7 @@ clear_var_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 149cae6581..d1678bf96f 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -132,7 +132,7 @@ clear_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 21f63ecae5..4b85c0732b 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -107,7 +107,7 @@ clear_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 8d02e5d2ec..2c19453740 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -114,7 +114,7 @@ clear_fixed_var_mtrr_out: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax @@ -160,7 +160,7 @@ clear_fixed_var_mtrr_out: #ifdef CARTEST /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %esi andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei @@ -241,7 +241,7 @@ testok: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index 935108fd73..802ecedd13 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -25,7 +25,7 @@ config USBDEBUG It also requires a USB2 controller which supports the EHCI Debug Port capability. - See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list + See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers. If unsure, say N. diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README index 1d7bbdc822..ffcbcc021f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ b/src/mainboard/supermicro/h8dmr_fam10/README @@ -17,6 +17,6 @@ while. Again, not an issue specific to this port. * to avoid very slow LZMA decompression I use this port with LZMA compression disabled in CBFS. I'm not sure what's causing this particular slowness. -See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html +See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html Ward, 2009-09-22 diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 7b7140e105..f59eedb367 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -46,7 +46,7 @@ /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: - * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. + * https://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. */ static int acpi_is_wakeup_early_via_vx800(void) { @@ -527,7 +527,7 @@ void main(unsigned long bist) #if PAYLOAD_IS_SEABIOS == 1 if (boot_mode == 3) { /* An idea of Libo.Feng at amd.com in - * http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html + * https://www.coreboot.org/pipermail/coreboot/2008-December/043111.html * * I want move the 1M data, I have to set some MTRRs myself. * Setting MTRR before back memory save s3 resume time about diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index edde13b6f2..cc8c328390 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -313,7 +313,7 @@ static void set_dram_timing(void) * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided * * See also: - * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html + * https://www.coreboot.org/pipermail/coreboot/2009-May/047966.html */ static void set_dram_buffer_strength(void) { diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 24720d14a3..d1bb3eef48 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -134,7 +134,7 @@ clear_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |