diff options
Diffstat (limited to 'src')
34 files changed, 121 insertions, 260 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e453aa432f..b610904a9e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -118,10 +118,11 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 9ff8ceb62d..254eff853c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -247,7 +247,9 @@ chip soc/intel/skylake register "PcieRpHotPlug[6]" = "1" # PL2 override 91W - register "tdp_pl2_override" = "91" + register "power_limits_config" = "{ + .tdp_pl2_override = 91, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 564b45dfc6..3b1f22c8c1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -250,8 +250,10 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + }" register "tcc_offset" = "10" device cpu_cluster 0 on diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6627c47481..c86be82c68 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -9,6 +9,7 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> +#include <intelblocks/power_limit.h> #include <variant/gpio.h> #include <smbios.h> #include <soc/gpio.h> @@ -99,7 +100,7 @@ static uint8_t board_sku_id(void) * | n (U22) | 29 | .9n | .9n | x(43) | * +-------------+-----+---------+---------+-------+ */ -static void mainboard_set_power_limits(config_t *conf) +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) { enum usb_chg_type type; u32 watts; @@ -215,9 +216,11 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { + struct soc_power_limits_config *soc_conf; config_t *conf = config_of_soc(); - mainboard_set_power_limits(conf); + soc_conf = &conf->power_limits_config; + mainboard_set_power_limits(soc_conf); dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index f02accec71..b8455fe9e9 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -325,8 +325,10 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" + register "power_limits_config" = "{ + .tdp_psyspl2 = 90, + .psys_pmax = 120, + }" register "tcc_offset" = "6" # TCC of 94C device cpu_cluster 0 on diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index f978240323..bfa260e9e9 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -17,7 +17,9 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader - register "psys_pmax" = "151" + register "power_limits_config" = "{ + .psys_pmax = 151, + }" device domain 0 on device pci 14.0 on diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4e85e21111..f7be80d460 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -99,7 +99,9 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index ce364801ca..7bee2e2a48 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -25,7 +25,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb index ae32b3dabf..9aeb78afa7 100644 --- a/src/mainboard/google/glados/variants/cave/overridetree.cb +++ b/src/mainboard/google/glados/variants/cave/overridetree.cb @@ -18,7 +18,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2 # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb index c6ccd208aa..ad3ae391c7 100644 --- a/src/mainboard/google/glados/variants/chell/overridetree.cb +++ b/src/mainboard/google/glados/variants/chell/overridetree.cb @@ -16,7 +16,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb index 1bc69abb17..c510e920a0 100644 --- a/src/mainboard/google/glados/variants/glados/overridetree.cb +++ b/src/mainboard/google/glados/variants/glados/overridetree.cb @@ -18,7 +18,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2 # PL2 override 15W - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + }" # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index b7ab523877..ce943c486c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -70,9 +70,11 @@ chip soc/intel/skylake register "PmTimerDisabled" = "1" register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "15" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 7974a289d3..ea7ee8fdc4 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> #define PL2_AML 18 #define PL2_KBL 15 @@ -25,8 +26,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 77725349e7..0f3cc0443f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -267,9 +267,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e4d148c3e2..4fa41c55ca 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -288,7 +288,9 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tcc_offset" = "3" # TCC of 97C - register "psys_pmax" = "101" + register "power_limits_config" = "{ + .psys_pmax = 101, + }" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 648e0d0647..8d5d0c482b 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -10,6 +10,7 @@ #include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/mp_init.h> +#include <intelblocks/power_limit.h> #include <smbios.h> #include <soc/ramstage.h> #include <string.h> @@ -279,8 +280,11 @@ void variant_devtree_update(void) break; } + struct soc_power_limits_config *soc_conf; + soc_conf = &cfg->power_limits_config; + /* Update PL2 based on SKU. */ - cfg->tdp_pl2_override = get_pl2(pl2_id); + soc_conf->tdp_pl2_override = get_pl2(pl2_id); /* Overwrite settings for different projects based on OEM ID*/ oem_index = find_sku_mapping(read_oem_id()); diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index c3404bf4f8..c55562d0ec 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -288,9 +288,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 96fcc39e65..8819350dce 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -66,9 +66,11 @@ chip soc/intel/skylake # Set speed_shift_enable to 1 to enable P-States, and 0 to disable register "speed_shift_enable" = "1" - register "tdp_pl1_override" = "7" - register "tdp_pl2_override" = "18" - register "psys_pmax" = "45" + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" register "pirqa_routing" = "PCH_IRQ11" diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 8d72144f9b..1482b3458f 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> /* PL2 limit in watts for AML and KBL */ #define PL2_AML 18 @@ -26,8 +27,10 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { + struct soc_power_limits_config *soc_conf; config_t *cfg = config_of_soc(); + soc_conf = &cfg->power_limits_config; /* Update PL2 based on CPU */ - cfg->tdp_pl2_override = get_pl2(); + soc_conf->tdp_pl2_override = get_pl2(); } diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 65578708ad..de7023dacb 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -246,9 +246,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 18W for AML-Y - register "tdp_pl2_override" = "18" + register "power_limits_config" = "{ + .tdp_pl2_override = 18, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 146d8d2c19..8c22adea2f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -268,9 +268,11 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "psys_pmax" = "45" # PL2 override 15W for KBL-Y - register "tdp_pl2_override" = "15" + register "power_limits_config" = "{ + .tdp_pl2_override = 15, + .psys_pmax = 45, + }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 436a4ed7d4..fa502834af 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -111,7 +111,9 @@ chip soc/intel/skylake }" # PL2 override 60W - register "tdp_pl2_override" = "60" + register "power_limits_config" = "{ + .tdp_pl2_override = 60, + }" # Power Limit Related register "PowerLimit4" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 46d7929d21..91abfe6f03 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -156,7 +156,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Use default SD card detect GPIO configuration #register "sdcard_cd_gpio_default" = "GPP_D10" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ab306149de..acd197bff4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -166,7 +166,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index f4ccb1bd5a..4811a41491 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -213,7 +213,9 @@ chip soc/intel/skylake }" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f54b877f18..95874bb5fa 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -171,7 +171,9 @@ chip soc/intel/skylake register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 854f5db48a..a439e02689 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -168,7 +168,9 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" # PL2 override 25W - register "tdp_pl2_override" = "25" + register "power_limits_config" = "{ + .tdp_pl2_override = 25, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index b55ef41f2d..7d54d33d8e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,10 +170,11 @@ chip soc/intel/skylake register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? # PL1 override 25W - register "tdp_pl1_override" = "25" - # PL2 override 44W - register "tdp_pl2_override" = "44" + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 44, + }" # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0a5daeaa82..55437f356e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -73,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ce566cf7b5..b14bb72a7b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -14,6 +14,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/mp_init.h> #include <intelblocks/pcie_rp.h> +#include <intelblocks/power_limit.h> #include <intelblocks/xdci.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> @@ -124,10 +125,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) config = config_of_soc(); mainboard_silicon_init_params(params); + + struct soc_power_limits_config *soc_confg; + config_t *confg = config_of_soc(); + soc_confg = &confg->power_limits_config; /* Set PsysPmax if it is available from DT */ - if (config->psys_pmax) { + if (soc_confg->psys_pmax) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; + tconfig->PsysPmax = soc_confg->psys_pmax * 8; printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index eb6cf9d7bc..92cd1bad85 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -11,6 +11,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/power_limit.h> #include <stdint.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -33,6 +34,9 @@ struct soc_intel_skylake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* IGD panel configuration */ unsigned int gpu_pp_up_delay_ms; unsigned int gpu_pp_down_delay_ms; @@ -100,27 +104,6 @@ struct soc_intel_skylake_config { /* Package PL4 power limit in Watts */ u32 PowerLimit4; - /* PL2 Override value in Watts */ - u32 tdp_pl2_override; - /* PL1 Override value in Watts */ - u32 tdp_pl1_override; - - /* SysPL2 Value in Watts */ - u32 tdp_psyspl2; - - /* SysPL3 Value in Watts */ - u32 tdp_psyspl3; - /* SysPL3 window size */ - u32 tdp_psyspl3_time; - /* SysPL3 duty cycle */ - u32 tdp_psyspl3_dutycycle; - - /* PL4 Value in Watts */ - u32 tdp_pl4; - - /* Estimated maximum platform power in Watts */ - u16 psys_pmax; - /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1aba7f6a47..28572e5948 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -30,196 +30,6 @@ #include "chip.h" -/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ -static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, -}; - -/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ -static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, -}; - -/* - * Configure processor power limits if possible - * This must be done AFTER set of BIOS_RESET_CPL - */ -void set_power_limits(u8 power_limit_1_time) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - msr_t limit; - unsigned int power_unit; - unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; - u8 power_limit_1_val; - - config_t *conf = config_of_soc(); - - if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) - power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; - - if (!(msr.lo & PLATFORM_INFO_SET_TDP)) - return; - - /* Get units */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 1 << (msr.lo & 0xf); - - /* Get power defaults for this SKU */ - msr = rdmsr(MSR_PKG_POWER_SKU); - tdp = msr.lo & 0x7fff; - min_power = (msr.lo >> 16) & 0x7fff; - max_power = msr.hi & 0x7fff; - max_time = (msr.hi >> 16) & 0x7f; - - printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); - - if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) - power_limit_1_time = power_limit_time_msr_to_sec[max_time]; - - if (min_power > 0 && tdp < min_power) - tdp = min_power; - - if (max_power > 0 && tdp > max_power) - tdp = max_power; - - power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; - - /* Set long term power limit to TDP */ - limit.lo = 0; - tdp_pl1 = ((conf->tdp_pl1_override == 0) ? - tdp : (conf->tdp_pl1_override * power_unit)); - limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK); - - /* Set PL1 Pkg Power clamp bit */ - limit.lo |= PKG_POWER_LIMIT_CLAMP; - - limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - - /* Set short term power limit to 1.25 * TDP if no config given */ - limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); - printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit); - limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - /* Power limit 2 time is only programmable on server SKU */ - wrmsr(MSR_PKG_POWER_LIMIT, limit); - - /* Set PL2 power limit values in MCHBAR and disable PL1 */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; - - /* Set PsysPl2 */ - if (conf->tdp_psyspl2) { - limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); - limit.hi = 0; - printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", - conf->tdp_psyspl2); - limit.hi |= (conf->tdp_psyspl2 * power_unit) & - PKG_POWER_LIMIT_MASK; - limit.hi |= PKG_POWER_LIMIT_CLAMP; - limit.hi |= PKG_POWER_LIMIT_EN; - - wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); - } - - /* Set PsysPl3 */ - if (conf->tdp_psyspl3) { - limit = rdmsr(MSR_PL3_CONTROL); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n", - conf->tdp_psyspl3); - limit.lo |= (conf->tdp_psyspl3 * power_unit) & - PKG_POWER_LIMIT_MASK; - /* Enable PsysPl3 */ - limit.lo |= PKG_POWER_LIMIT_EN; - /* set PsysPl3 time window */ - limit.lo |= (conf->tdp_psyspl3_time & - PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; - /* set PsysPl3 duty cycle */ - limit.lo |= (conf->tdp_psyspl3_dutycycle & - PKG_POWER_LIMIT_DUTYCYCLE_MASK) << - PKG_POWER_LIMIT_DUTYCYCLE_SHIFT; - wrmsr(MSR_PL3_CONTROL, limit); - } - - /* Set Pl4 */ - if (conf->tdp_pl4) { - limit = rdmsr(MSR_VR_CURRENT_CONFIG); - limit.lo = 0; - printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n", - conf->tdp_pl4); - limit.lo |= (conf->tdp_pl4 * power_unit) & - PKG_POWER_LIMIT_MASK; - wrmsr(MSR_VR_CURRENT_CONFIG, limit); - } - - /* Set DDR RAPL power limit by copying from MMIO to MSR */ - msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); - msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); - wrmsr(MSR_DDR_RAPL_LIMIT, msr); - - /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { - limit.hi = 0; - limit.lo = cpu_get_tdp_nominal_ratio(); - wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); - } -} - static void configure_thermal_target(void) { config_t *conf = config_of_soc(); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 43710b6b98..740b3d3fb0 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -34,9 +34,6 @@ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ (IRTL_1024_NS >> 10)) -/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); - /* CPU identification */ u32 cpu_family_model(void); u32 cpu_stepping(void); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index a4d7330a47..8e58bf6669 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -4,6 +4,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -60,6 +61,9 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -68,7 +72,9 @@ void soc_systemagent_init(struct device *dev) /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, |