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-rw-r--r--src/mainboard/nokia/ip530/Kconfig2
-rw-r--r--src/mainboard/nokia/ip530/devicetree.cb53
-rw-r--r--src/mainboard/nokia/ip530/irq_tables.c70
-rw-r--r--src/mainboard/nokia/ip530/mainboard.c37
4 files changed, 88 insertions, 74 deletions
diff --git a/src/mainboard/nokia/ip530/Kconfig b/src/mainboard/nokia/ip530/Kconfig
index 31c6216923..0eac00a3ab 100644
--- a/src/mainboard/nokia/ip530/Kconfig
+++ b/src/mainboard/nokia/ip530/Kconfig
@@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_SMSC_SMSCSUPERIO
select SOUTHBRIDGE_TI_PCI1X2X
select DRIVERS_DEC_21143
- select BOARD_ROMSIZE_KB_256
+ select BOARD_ROMSIZE_KB_512
select PIRQ_ROUTE
select HAVE_PIRQ_TABLE
select UDELAY_TSC
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
index 673e0cb10d..3cfbc8fb0f 100644
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ b/src/mainboard/nokia/ip530/devicetree.cb
@@ -40,10 +40,55 @@ chip northbridge/intel/i440bx # Northbridge
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 3f0.6 on end # RTC
- device pnp 3f0.7 off end # PS/2 keyboard / mouse (No connector)
- device pnp 3f0.8 on end # AUX I/O
- device pnp 3f0.a off end # ACPI (No support yet)
+ device pnp 3f0.6 on # RTC
+ irq 0x63 = 0x72
+ end
+ device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector)
+ end
+ device pnp 3f0.8 on # AUX I/O
+ irq 0x24 = 0x84 # OSC
+
+ irq 0xB2 = 0x0C # Soft power status 1
+ irq 0xB3 = 0x05 # Soft power status 2
+ irq 0xC0 = 0x03 # IRQ MUX control
+
+ irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable
+ irq 0xCA = 0x09 # GP52 = IRQ8 (output)
+ irq 0xCB = 0x01 # GP53 = nROMCS (output)
+ irq 0xCC = 0x11 # GP54 = (I/O) input
+ irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
+
+ irq 0xD0 = 0x08 # GP60 = IRQ1
+ irq 0xD1 = 0x08 # GP61 = IRQ3
+ irq 0xD2 = 0x08 # GP62 = IRQ4
+ irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board
+ irq 0xD4 = 0x11 # GP64 = (I/O) input
+ irq 0xD5 = 0x11 # GP65 = (I/O) input
+ irq 0xD6 = 0x08 # GP66 = IRQ8
+ irq 0xD7 = 0x11 # GP67 = (I/O) input
+ irq 0xFA = 0x00 # read/write GP6x lines (0x88)
+
+ irq 0xE0 = 0x00 # GP10 (I/O) = output
+ irq 0xE1 = 0x01 # GP11 (I/O) = input
+ irq 0xE2 = 0x08 # GP12 = P17
+ irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low
+ irq 0xE4 = 0x00 # GP14 (I/O) = output
+ irq 0xE5 = 0x00 # GP15 (I/O) = output
+ irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open
+ irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low
+ irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
+
+ irq 0xEF = 0x00 # GP_INT2 disable
+ irq 0xF0 = 0x00 # GP_INT1 disable
+ irq 0xF1 = 0x00 # WDT_UNITS
+ irq 0xF2 = 0x00 # WDT_VAL
+ irq 0xF3 = 0x00 # WDT_CFG
+ irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt)
+ end
+ device pnp 3f0.a off # ACPI (No support yet)
+ # irq 0x60 = 0x0C
+ # irq 0x61 = 0x80
+ end
end
end
device pci 7.1 on end # IDE
diff --git a/src/mainboard/nokia/ip530/irq_tables.c b/src/mainboard/nokia/ip530/irq_tables.c
index 21c8805ebd..091a44f424 100644
--- a/src/mainboard/nokia/ip530/irq_tables.c
+++ b/src/mainboard/nokia/ip530/irq_tables.c
@@ -20,6 +20,8 @@
#include <arch/pirq_routing.h>
+#define PIRQ_IRQ_MASK 0x0c60
+
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
@@ -31,46 +33,51 @@ const struct irq_routing_table intel_irq_routing_table = {
0x122e, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x44, /* Checksum */
+ 0xD7, /* Checksum */
{
/**
- * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
+ * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
+ * FEDCBA9876543210
+ * 0x1E20 = 0001111000100000
+ * 0x0C60 = 0000110001100000
*/
- // Southbridge 82371
- { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ // Southbridge 82371EB, INTD = 0x63
+ { 0x00, (0x07 << 3) | 0x0, {{0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
// On-board PCI-to-PCI bridge
- { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
- // ETH1 on front panel
- { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
- // ETH2 on front panel
- { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
- // ETH3 on front panel
- { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
- // ETH4 on front panel
- { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
- // PCMCIA/Cardbus controller
- { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ { 0x01, (0x00 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ // ETH1 on front panel, INTA = 0x62 = ok
+ { 0x00, (0x0d << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+
+ // ETH2 on front panel, 0x63
+ { 0x00, (0x0e << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ // ETH3 on front panel = 0x60
+ { 0x02, (0x04 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+
+ // ETH4 on front panel, INTA = 0x61 = ok
+ { 0x02, (0x05 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ // PCMCIA/Cardbus controller, INTA = 0x60 = ok, INTB = 0x61 = ok
+ { 0x00, (0x0f << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
// Bridge for slot 1 (top)
- { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
+ { 0x02, (0x07 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x64, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
// PCI compact slots 1 (top)
- { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
- { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
- { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
- { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
+ { 0x03, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x1, 0x0 },
+ { 0x03, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x2, 0x0 },
+ { 0x03, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x3, 0x0 },
+ { 0x03, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x4, 0x0 },
// Bridge for slot 2 (middle)
- { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ { 0x02, (0x06 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
// PCI compact slots 2 (middle)
- { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
- { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
- { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
- { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
+ { 0x04, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x5, 0x0 },
+ { 0x04, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x6, 0x0 },
+ { 0x04, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x7, 0x0 },
+ { 0x04, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x8, 0x0 },
// Bridge for slot 3 (bottom)
- { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ { 0x00, (0x10 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
// PCI compact slots 3 (bottom)
- { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
- { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
- { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
- { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
+ { 0x05, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x9, 0x0 },
+ { 0x05, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0xA, 0x0 },
+ { 0x05, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0xB, 0x0 },
+ { 0x05, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0xC, 0x0 },
}
};
@@ -81,10 +88,9 @@ unsigned long write_pirq_routing_table(unsigned long addr)
/**
* TODO: This stub function is here until the point is solved in the
- * main code of coreboot. see also arch/x86/boot/pirq_tables.c
+ * main code of coreboot. See also arch/x86/boot/pirq_tables.c.
*/
void pirq_assign_irqs(const unsigned char pIntAtoD[4])
{
return;
}
-
diff --git a/src/mainboard/nokia/ip530/mainboard.c b/src/mainboard/nokia/ip530/mainboard.c
index 61537c8be8..b0dd27bdb8 100644
--- a/src/mainboard/nokia/ip530/mainboard.c
+++ b/src/mainboard/nokia/ip530/mainboard.c
@@ -20,44 +20,7 @@
#include <device/device.h>
#include "chip.h"
-#include <device/pci_def.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#define OUTB outb
-#define INB inb
-
-/*
-* Taken from flashrom project
-* Generic Super I/O helper functions
-*/
-static uint8_t sio_read(uint16_t port, uint8_t reg)
-{
- OUTB( reg, port );
- return ( INB( port + 1 ) );
-}
-
-static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
-{
- OUTB( reg, port );
- OUTB( data, port + 1 );
- return;
-}
-
-static void nokia_ip530_board_enable( device_t dev )
-{
- print_debug( "Setting up IP530-Super I/O devices\n");
- sio_write( 0x20, 0x03, 0x80 );
- printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
- sio_write( 0x20, 0x22, 0x30 );
- printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
- sio_write( 0x20, 0x24, 0x84 );
- printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
- return;
-}
struct chip_operations mainboard_ops = {
CHIP_NAME("Nokia IP530 Mainboard")
- .enable_dev = nokia_ip530_board_enable,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 00:18:30 +0000