diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/gpio.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 5c4f61342e..da70da15d1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -139,10 +139,10 @@ static const struct pad_config gpio_table[] = { /* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */ PAD_NC(GPP_C7, NONE), - /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D0, NONE, DEEP, EDGE_SINGLE, INVERT), - /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_INT_ODL */ - PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, LEVEL), + /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ + PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL), + /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */ PAD_NC(GPP_D2, NONE), /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> ISH_ACCEL_MB_INT_L (NC) */ diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h index 54321e54f6..0e69fb32d8 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h +++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h @@ -8,13 +8,13 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -/* EC wake is EC_PCH_INT which is routed to GPP_D1 pin */ -#define GPE_EC_WAKE GPE0_DW1_01 +/* EC wake is EC_PCH_INT which is routed to GPP_D0 pin */ +#define GPE_EC_WAKE GPE0_DW1_00 /* WP signal to PCH */ #define GPIO_PCH_WP GPP_E8 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_D17 /* GPIO IRQ for tight timestamps / wake support */ -#define EC_SYNC_IRQ GPP_D1_IRQ +#define EC_SYNC_IRQ GPP_D0_IRQ #endif /* __BASEBOARD_GPIO_H__ */ |