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-rw-r--r--src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c18
-rw-r--r--src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c24
-rw-r--r--src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h21
3 files changed, 21 insertions, 42 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index 8d55db6934..c6e63add4e 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -18,45 +18,45 @@ static const fsp_dxio_descriptor dxio_descriptors[] = {
// NVME SSD
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = NVME_START_LANE,
- .end_logical_lane = NVME_END_LANE,
+ .start_logical_lane = 4,
+ .end_logical_lane = 5,
.device_number = 1,
.function_number = 7,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = NVME_CLKREQ,
+ .clk_req = CLK_REQ2,
.clk_pm_support = true,
},
{
// WLAN
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = WLAN_START_LANE,
- .end_logical_lane = WLAN_END_LANE,
+ .start_logical_lane = 0,
+ .end_logical_lane = 0,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = WLAN_CLKREQ,
+ .clk_req = CLK_REQ0,
.clk_pm_support = true,
},
{
// SD Reader
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = SD_START_LANE,
- .end_logical_lane = SD_END_LANE,
+ .start_logical_lane = 1,
+ .end_logical_lane = 1,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = SD_CLKREQ,
+ .clk_req = CLK_REQ1,
}
};
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
index 75c2211ee9..26a5d33a1b 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
@@ -31,7 +31,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = {
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = NVME_CLKREQ,
+ .clk_req = CLK_REQ4,
},
{
// WLAN
@@ -45,7 +45,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = {
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = WLAN_CLKREQ,
+ .clk_req = CLK_REQ0,
.clk_pm_support = true,
},
{
@@ -60,7 +60,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = {
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = SD_CLKREQ,
+ .clk_req = CLK_REQ1,
}
};
@@ -69,45 +69,45 @@ static const fsp_dxio_descriptor dali_dxio_descriptors[] = {
// NVME SSD
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = NVME_START_LANE,
- .end_logical_lane = NVME_END_LANE,
+ .start_logical_lane = 0,
+ .end_logical_lane = 1,
.device_number = 1,
.function_number = 7,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = NVME_CLKREQ,
+ .clk_req = CLK_REQ4,
.clk_pm_support = true,
},
{
// WLAN
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = WLAN_START_LANE,
- .end_logical_lane = WLAN_END_LANE,
+ .start_logical_lane = 4,
+ .end_logical_lane = 4,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = WLAN_CLKREQ,
+ .clk_req = CLK_REQ0,
.clk_pm_support = true,
},
{
// SD Reader
.port_present = true,
.engine_type = PCIE_ENGINE,
- .start_logical_lane = SD_START_LANE,
- .end_logical_lane = SD_END_LANE,
+ .start_logical_lane = 5,
+ .end_logical_lane = 5,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
- .clk_req = SD_CLKREQ,
+ .clk_req = CLK_REQ1,
}
};
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
index 84433e0622..389f0e832a 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
@@ -7,31 +7,10 @@
#include <soc/gpio.h>
#include <platform_descriptors.h>
-#define WLAN_CLKREQ CLK_REQ0
-#define SD_CLKREQ CLK_REQ1
-
-#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ)
-#define NVME_START_LANE 4
-#define NVME_END_LANE 5
-#define WLAN_START_LANE 0
-#define WLAN_END_LANE 0
-#define SD_START_LANE 1
-#define SD_END_LANE 1
-#else
-#define NVME_START_LANE 0
-#define NVME_END_LANE 1
-#define WLAN_START_LANE 4
-#define WLAN_END_LANE 4
-#define SD_START_LANE 5
-#define SD_END_LANE 5
-#endif
-
#if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)
#define EC_IN_RW_OD GPIO_130
-#define NVME_CLKREQ CLK_REQ4
#else
#define EC_IN_RW_OD GPIO_11
-#define NVME_CLKREQ CLK_REQ2
#endif
/* SPI Write protect */