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-rw-r--r--src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
index a302e4f1c4..fc21f18d74 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
@@ -8,13 +8,11 @@ chip soc/intel/alderlake
},
}"
- # FSP Memory
- register "sagv" = "SaGv_Enabled"
-
- # FSP Silicon
- register "eist_enable" = "true"
- register "cnvi_bt_core" = "true"
+ # FSP UPDs
register "cnvi_bt_audio_offload" = "true"
+ register "cnvi_bt_core" = "true"
+ register "eist_enable" = "true"
+ register "sagv" = "SaGv_Enabled"
# Serial I/O
register "serial_io_i2c_mode" = "{