diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/hp/z220_series/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 4611bec140..ea8fad9320 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -22,6 +22,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Host bridge Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on end # Internal graphics VGA controller + device pci 06.0 off end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "docking_supported" = "0" @@ -47,8 +48,8 @@ chip northbridge/intel/sandybridge device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 on end # PCI bridge device pci 1f.0 on # LPC bridge PCI-LPC bridge diff --git a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb index 2e46d2a0b6..55bdaac23a 100644 --- a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x103c 0x1791 inherit + device pci 06.0 on end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x register "sata_port_map" = "0x3f" @@ -10,6 +11,8 @@ chip northbridge/intel/sandybridge device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 on end # PCIe Port #4 device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 end end end |