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-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c2
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/devicetree.cb1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index bbb51e49dc..36bb419d41 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -35,6 +35,4 @@ void OemPostParams(AMD_POST_PARAMS *PostParams)
{
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
- /* disable memory clear for pstore memory storage and boot time */
- PostParams->MemConfig.EnableMemClr = FALSE;
}
diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
index 4376011797..c4535225e2 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
@@ -18,6 +18,7 @@ chip soc/amd/stoneyridge
{
{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
}"
+ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
device cpu_cluster 0 on
device lapic 10 on end