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-rw-r--r--src/include/device/pci_ids.h10
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c10
2 files changed, 20 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 475d0a84c8..d99f307bd9 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2768,8 +2768,18 @@
#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1
/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */
+#define PCI_DID_INTEL_IBEXPEAK_LPC_P55 0x3b02
+#define PCI_DID_INTEL_IBEXPEAK_LPC_PM55 0x3b03
+#define PCI_DID_INTEL_IBEXPEAK_LPC_H55 0x3b06
#define PCI_DID_INTEL_IBEXPEAK_LPC_QM57 0x3b07
+#define PCI_DID_INTEL_IBEXPEAK_LPC_H57 0x3b08
#define PCI_DID_INTEL_IBEXPEAK_LPC_HM55 0x3b09
+#define PCI_DID_INTEL_IBEXPEAK_LPC_Q57 0x3b0a
+#define PCI_DID_INTEL_IBEXPEAK_LPC_HM57 0x3b0b
+#define PCI_DID_INTEL_IBEXPEAK_LPC_QS57 0x3b0f
+#define PCI_DID_INTEL_IBEXPEAK_LPC_3400 0x3b12
+#define PCI_DID_INTEL_IBEXPEAK_LPC_3420 0x3b14
+#define PCI_DID_INTEL_IBEXPEAK_LPC_3450 0x3b16
#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1 0x3b28
#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI 0x3b29
#define PCI_DID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2 0x3b2e
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index ed0e03c5f1..706df254d7 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -563,8 +563,18 @@ static struct device_operations device_ops = {
};
static const unsigned short pci_device_ids[] = {
+ PCI_DID_INTEL_IBEXPEAK_LPC_P55,
+ PCI_DID_INTEL_IBEXPEAK_LPC_PM55,
+ PCI_DID_INTEL_IBEXPEAK_LPC_H55,
PCI_DID_INTEL_IBEXPEAK_LPC_QM57,
+ PCI_DID_INTEL_IBEXPEAK_LPC_H57,
PCI_DID_INTEL_IBEXPEAK_LPC_HM55,
+ PCI_DID_INTEL_IBEXPEAK_LPC_Q57,
+ PCI_DID_INTEL_IBEXPEAK_LPC_HM57,
+ PCI_DID_INTEL_IBEXPEAK_LPC_QS57,
+ PCI_DID_INTEL_IBEXPEAK_LPC_3400,
+ PCI_DID_INTEL_IBEXPEAK_LPC_3420,
+ PCI_DID_INTEL_IBEXPEAK_LPC_3450,
0
};