diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/fatcat/Kconfig | 35 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/dsdt.asl | 30 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/mainboard.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb | 64 | ||||
| -rw-r--r-- | src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h | 2 |
5 files changed, 117 insertions, 16 deletions
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index cf4233a0d3..d2c501938e 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -3,36 +3,51 @@ config BOARD_GOOGLE_FATCAT_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SOUNDWIRE_ALC722 select DRIVERS_SPI_ACPI + select DUMP_SMBIOS_TYPE17 + select EC_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_SKUID select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI + select GENERATE_SMBIOS_TABLES select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select I2C_TPM select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_DISABLE_STAGE_CACHE select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_EC_REGION select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE - select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_PANTHERLAKE_U_H + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION config BOARD_GOOGLE_BASEBOARD_FATCAT def_bool n select BOARD_GOOGLE_FATCAT_COMMON select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_INTEL_USB4_RETIMER select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_IOE_DIE_SUPPORT + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 @@ -42,8 +57,6 @@ config BOARD_GOOGLE_MODEL_FATCAT config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT - select HAVE_X86_64_SUPPORT - select USE_X86_64_SUPPORT if BOARD_GOOGLE_FATCAT_COMMON @@ -53,8 +66,8 @@ config BASEBOARD_DIR config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_FORCE_DEV_BOOT_USB - select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE @@ -72,14 +85,13 @@ config DEVICETREE config DIMM_SPD_SIZE default 512 -# FIXME: update below code as per board schematics config DRIVER_TPM_I2C_ADDR hex - default 0x0 + default 0x50 config DRIVER_TPM_I2C_BUS hex - default 0x0 + default 0x03 config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP @@ -103,13 +115,9 @@ config MEMORY_SOLDERDOWN select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select HAVE_SPD_IN_CBFS -config OVERRIDE_DEVICETREE - default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" - -# FIXME: update as per board schematics config TPM_TIS_ACPI_INTERRUPT int - default 0 + default 47 # GPE0_DW1_15 (GPP_D15) # FIXME: update as per board schematics config UART_FOR_CONSOLE @@ -123,6 +131,9 @@ config VARIANT_DIR string default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/fatcat/dsdt.asl b/src/mainboard/google/fatcat/dsdt.asl index 2c714d7a0c..03882c6327 100644 --- a/src/mainboard/google/fatcat/dsdt.asl +++ b/src/mainboard/google/fatcat/dsdt.asl @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <variant/ec.h> +#include <variant/gpio.h> DefinitionBlock( "dsdt.aml", @@ -9,8 +10,33 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20240917 ) { - /* TODO: Add ACPI code as per board design */ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/pantherlake/acpi/southbridge.asl> + #include <soc/intel/pantherlake/acpi/tcss.asl> + } + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* ChromeOS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c index 55b9e4c791..0d1fcd3c66 100644 --- a/src/mainboard/google/fatcat/mainboard.c +++ b/src/mainboard/google/fatcat/mainboard.c @@ -21,7 +21,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *confi variant_update_soc_chip_config(config); } -__weak void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) +void __weak variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { /* default implementation does nothing */ } diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 73b99dbc94..f73cae1f14 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -1,3 +1,65 @@ chip soc/intel/pantherlake - device domain 0 on end + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + + # Enable s0ix + register "s0ix_enable" = "false" + + # DPTF enable + register "dptf_enable" = "false" + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "pch_hda_dsp_enable" = "true" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_sdi_enable" = "{ true, false }" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref npu on end + device ref xhci on end + device ref pmc_shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref soc_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + end end diff --git a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h index e468198171..0e937dc0e0 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h +++ b/src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h @@ -6,5 +6,7 @@ #include <baseboard/gpio.h> /* TODO: Add GPIO as per fatcat board */ +/* Dummy pin number for ACPI table to build */ +#define GPE_EC_WAKE 0 #endif /* __MAINBOARD_GPIO_H__ */ |