4 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index c12d982166..f503d465e8 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_INT15
+	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
@@ -44,6 +45,11 @@ config BOARD_GOOGLE_SAMUS
 
 if BOARD_GOOGLE_BASEBOARD_AURON
 
+config VBOOT
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select VBOOT_LID_SWITCH
+	select VBOOT_VBNV_CMOS
+
 config MAINBOARD_DIR
 	default "google/auron"
 
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index c882bc7a78..4cbad81d09 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_JECHT
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
@@ -25,6 +26,9 @@ config BOARD_GOOGLE_TIDUS
 
 if BOARD_GOOGLE_BASEBOARD_JECHT
 
+config VBOOT
+	select VBOOT_VBNV_CMOS
+
 config MAINBOARD_DIR
 	default "google/jecht"
 
diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index b8b7e27c26..9977d3bd29 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -7,9 +7,13 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
+	select MAINBOARD_HAS_CHROMEOS
 	select MEMORY_MAPPED_TPM
 	select INTEL_INT15
 
+config VBOOT
+	select VBOOT_VBNV_CMOS
+
 config MAINBOARD_DIR
 	default "intel/wtm2"
 
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 3a5b5d52c1..61513e8b70 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -19,6 +19,25 @@ config BROADWELL_LPDDR3
 	  Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific
 	  LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit.
 
+config BROADWELL_VBOOT_IN_BOOTBLOCK
+	depends on VBOOT
+	bool "Start verstage in bootblock"
+	default y
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	help
+	  Broadwell can either start verstage in a separate stage
+	  right after the bootblock has run or it can start it
+	  after romstage for compatibility reasons.
+	  Broadwell however uses a mrc.bin to initialize memory which
+	  needs to be located at a fixed offset. Therefore even with
+	  a separate verstage starting after the bootblock that same
+	  binary is used meaning a jump is made from RW to the RO region
+	  and back to the RW region after the binary is done.
+
+config VBOOT
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
+
 config ECAM_MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
@@ -84,6 +103,13 @@ config MRC_BIN_ADDRESS
 	hex
 	default 0xfffa0000
 
+# The UEFI System Agent binary needs to be at a fixed offset in the flash
+# and can therefore only reside in the COREBOOT fmap region
+config RO_REGION_ONLY
+	string
+	depends on VBOOT
+	default "mrc.bin"
+
 endif # HAVE_MRC
 
 config HAVE_REFCODE_BLOB