1 files changed, 0 insertions, 45 deletions
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c
index 03bc17f185..ed9923f990 100644
--- a/src/mainboard/google/drallion/romstage.c
+++ b/src/mainboard/google/drallion/romstage.c
@@ -18,51 +18,6 @@
 #include <soc/romstage.h>
 #include <baseboard/variants.h>
 
-void __weak variant_mainboard_post_init_params(FSPM_UPD *mupd) {}
-
-static const struct cnl_mb_cfg memcfg = {
-	/* Access memory info through SMBUS. */
-	.spd[0] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa0},
-	},
-	.spd[1] = {.read_type = NOT_EXISTING},
-	.spd[2] = {
-		.read_type = READ_SMBUS,
-		.spd_spec = {.spd_smbus_address = 0xa4},
-	},
-	.spd[3] = {.read_type = NOT_EXISTING},
-
-	/*
-	 * The dqs_map arrays map the ddr4 pins to the SoC pins
-	 * for both channels.
-	 *
-	 * the index = pin number on ddr4 part
-	 * the value = pin number on SoC
-	 */
-	.dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7},
-	.dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7},
-
-	/* Baseboard uses 121, 81 and 100 rcomp resistors */
-	.rcomp_resistor = {121, 81, 100},
-
-	/*
-	 * Baseboard Rcomp target values.
-	 */
-	.rcomp_targets = {100, 40, 20, 20, 26},
-
-	/* Disable Early Command Training */
-	.ect = 0,
-
-	/* Base on board design */
-	.vref_ca_config = 2,
-};
-
-const struct cnl_mb_cfg * __weak get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg)
-{
-	return &memcfg;
-}
-
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	struct cnl_mb_cfg board_memcfg;