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-rw-r--r--src/console/Kconfig10
-rw-r--r--src/cpu/allwinner/a10/uart.c2
-rw-r--r--src/cpu/allwinner/a10/uart_console.c2
-rw-r--r--src/cpu/ti/am335x/uart.c4
-rw-r--r--src/drivers/uart/pl011.c2
-rw-r--r--src/drivers/uart/uart8250io.c4
-rw-r--r--src/drivers/uart/uart8250mem.c4
-rw-r--r--src/include/console/uart.h11
-rw-r--r--src/soc/broadcom/cygnus/ns16550.c2
-rw-r--r--src/soc/imgtec/pistachio/uart.c4
-rw-r--r--src/soc/mediatek/mt8173/uart.c4
-rw-r--r--src/soc/nvidia/tegra124/uart.c2
-rw-r--r--src/soc/nvidia/tegra210/uart.c2
-rw-r--r--src/soc/qualcomm/ipq40xx/uart.c2
-rw-r--r--src/soc/samsung/exynos5250/uart.c4
-rw-r--r--src/soc/samsung/exynos5420/uart.c4
16 files changed, 42 insertions, 21 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig
index c0e4a8c8b0..0421f6ba4c 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -76,6 +76,14 @@ depends on UART_FOR_CONSOLE = 2
comment "Serial port base address = 0x2e8"
depends on UART_FOR_CONSOLE = 3
+config UART_OVERRIDE_BAUDRATE
+ boolean
+ help
+ Set to "y" when the platform overrides the baudrate by providing
+ a get_uart_baudrate routine.
+
+if !UART_OVERRIDE_BAUDRATE
+
choice
prompt "Baud rate"
default CONSOLE_SERIAL_115200
@@ -129,6 +137,8 @@ config TTYS0_BAUD
help
Map the Baud rates to an integer.
+endif
+
# TODO: Allow user-friendly selection of settings other than 8n1.
config TTYS0_LCS
int
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index f7c2db99b3..9bcedeb49e 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -105,7 +105,7 @@ void uart_init(int idx)
struct a10_uart *uart_base = uart_platform_baseptr(idx);
/* Use default 8N1 encoding */
- a10_uart_configure(uart_base, CONFIG_TTYS0_BAUD,
+ a10_uart_configure(uart_base, get_uart_baudrate(),
8, UART_PARITY_NONE, 1);
a10_uart_enable_fifos(uart_base);
}
diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c
index 03d41228bc..363a41a129 100644
--- a/src/cpu/allwinner/a10/uart_console.c
+++ b/src/cpu/allwinner/a10/uart_console.c
@@ -44,7 +44,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = 0;
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index 47b9a3d5cd..38a13ac268 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -163,7 +163,7 @@ void uart_init(int idx)
{
struct am335x_uart *uart = uart_platform_baseptr(idx);
uint16_t div = (uint16_t) uart_baudrate_divisor(
- CONFIG_TTYS0_BAUD, uart_platform_refclk(), 16);
+ get_uart_baudrate(), uart_platform_refclk(), 16);
am335x_uart_init(uart, div);
}
@@ -189,7 +189,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 2;
lb_add_serial(&serial, data);
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index e690a9afb5..415dce13bc 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -51,7 +51,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index ace2c59fd5..94970f9c7d 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -107,7 +107,7 @@ void uart_init(int idx)
{
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250IO_SKIP_INIT)) {
unsigned int div;
- div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+ div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
uart8250_init(uart_platform_base(idx), div);
}
@@ -134,7 +134,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 1;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 9eb50cb4b1..b73a428b9b 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -119,7 +119,7 @@ void uart_init(int idx)
return;
unsigned int div;
- div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+ div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
uart8250_mem_init(base, div);
}
@@ -156,7 +156,7 @@ void uart_fill_lb(void *data)
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
if (!serial.baseaddr)
return;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
serial.regwidth = sizeof(uint32_t);
else
diff --git a/src/include/console/uart.h b/src/include/console/uart.h
index 0dccd00d43..3bd390e75b 100644
--- a/src/include/console/uart.h
+++ b/src/include/console/uart.h
@@ -23,6 +23,17 @@
* baudrate generator. */
unsigned int uart_platform_refclk(void);
+#if IS_ENABLED(CONFIG_UART_OVERRIDE_BAUDRATE)
+/* Return the baudrate, define this in your platform when using the above
+ configuration. */
+unsigned int get_uart_baudrate(void);
+#else
+static inline unsigned int get_uart_baudrate(void)
+{
+ return CONFIG_TTYS0_BAUD;
+}
+#endif
+
/* Returns the divisor value for a given baudrate.
* The formula to satisfy is:
* refclk / divisor = baudrate * oversample
diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c
index e7008274f6..68c4715cb3 100644
--- a/src/soc/broadcom/cygnus/ns16550.c
+++ b/src/soc/broadcom/cygnus/ns16550.c
@@ -120,7 +120,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = (uintptr_t)regs;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index df1a5ace04..f610f6a05d 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -124,7 +124,7 @@ void uart_init(int idx)
return;
unsigned int div;
- div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+ div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), 16);
uart8250_mem_init(base, div);
}
@@ -150,7 +150,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 1 << UART_SHIFT;
lb_add_serial(&serial, data);
diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c
index 36a279fa65..93625c4bfb 100644
--- a/src/soc/mediatek/mt8173/uart.c
+++ b/src/soc/mediatek/mt8173/uart.c
@@ -87,7 +87,7 @@ static void mtk_uart_init(void)
{
/* Use a hardcoded divisor for now. */
const unsigned uartclk = 26 * MHz;
- const unsigned baudrate = CONFIG_TTYS0_BAUD;
+ const unsigned baudrate = get_uart_baudrate();
const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */
unsigned highspeed, quot, divisor, remainder;
@@ -177,7 +177,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = UART0_BASE;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 0d5233788d..5cb8112d81 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -136,7 +136,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c
index 1c52687491..97dc740ebf 100644
--- a/src/soc/nvidia/tegra210/uart.c
+++ b/src/soc/nvidia/tegra210/uart.c
@@ -123,7 +123,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c
index 671a6d1281..4b0bffd216 100644
--- a/src/soc/qualcomm/ipq40xx/uart.c
+++ b/src/soc/qualcomm/ipq40xx/uart.c
@@ -297,7 +297,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = (uint32_t)UART1_DM_BASE;
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 1;
lb_add_serial(&serial, data);
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index 7ad6cbe6d9..78c72804c9 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
// All UARTs share the same clock.
uclk = clock_get_periph_rate(PERIPH_ID_UART3);
- val = uclk / CONFIG_TTYS0_BAUD;
+ val = uclk / get_uart_baudrate();
write32(&uart->ubrdiv, val / 16 - 1);
@@ -191,7 +191,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
lb_add_serial(&serial, data);
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index a38be07d13..146151ee5b 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
// All UARTs share the same clock.
uclk = clock_get_periph_rate(PERIPH_ID_UART3);
- val = uclk / CONFIG_TTYS0_BAUD;
+ val = uclk / get_uart_baudrate();
write32(&uart->ubrdiv, val / 16 - 1);
@@ -182,7 +182,7 @@ void uart_fill_lb(void *data)
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
- serial.baud = CONFIG_TTYS0_BAUD;
+ serial.baud = get_uart_baudrate();
serial.regwidth = 4;
serial.input_hertz = uart_platform_refclk();
serial.uart_pci_addr = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 10:39:12 +0000