diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 17 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me_mrc.c | 17 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/me.c | 31 | ||||
| -rw-r--r-- | src/southbridge/intel/common/me.h | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 |
8 files changed, 50 insertions, 32 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index e3ad885cb4..812b6c052e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -18,6 +18,7 @@ config SOUTH_BRIDGE_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SOUTHBRIDGE_INTEL_COMMON_ME select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 6320d2ea9f..09e5f39c9c 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -7,6 +7,7 @@ #include <delay.h> #include <device/pci_def.h> #include <halt.h> +#include <southbridge/intel/common/me.h> #include <string.h> #include <timestamp.h> #include "me.h" @@ -91,22 +92,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset, errorcode, opmode; diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c index 0b11fd0e81..180e466bd4 100644 --- a/src/southbridge/intel/bd82x6x/early_me_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c @@ -6,6 +6,7 @@ #include <delay.h> #include <device/pci_def.h> #include <halt.h> +#include <southbridge/intel/common/me.h> #include <string.h> #include "me.h" #include "pch.h" @@ -96,22 +97,6 @@ int intel_early_me_uma_size(void) return 0; } -static inline void set_global_reset(int enable) -{ - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; - - /* CF9GR indicates a Global Reset */ - if (enable) - etr3 |= ETR3_CF9GR; - else - etr3 &= ~ETR3_CF9GR; - - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); -} - int intel_early_me_init_done(u8 status) { u8 reset; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 1bdefd4b93..5d7a4ee784 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n +config SOUTHBRIDGE_INTEL_COMMON_ME + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_HPET def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index f11ffa6aef..adacc25a4b 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -7,6 +7,8 @@ all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET) += hpet.c +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME) += me.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c diff --git a/src/southbridge/intel/common/me.c b/src/southbridge/intel/common/me.c new file mode 100644 index 0000000000..d49508748a --- /dev/null +++ b/src/southbridge/intel/common/me.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/pci_ops.h> +#include <types.h> + +#include "me.h" + +#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) + +#define ETR3 0xac +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) +#define ETR3_CF9LOCK (1 << 31) + +void set_global_reset(const bool enable) +{ + u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + + /* Clear CF9 Without Resume Well Reset Enable */ + etr3 &= ~ETR3_CWORWRE; + + /* CF9GR indicates a Global Reset */ + if (enable) + etr3 |= ETR3_CF9GR; + else + etr3 &= ~ETR3_CF9GR; + + pci_write_config32(PCH_LPC_DEV, ETR3, etr3); +} diff --git a/src/southbridge/intel/common/me.h b/src/southbridge/intel/common/me.h new file mode 100644 index 0000000000..81c1b47bc9 --- /dev/null +++ b/src/southbridge/intel/common/me.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_HPET_H +#define SOUTHBRIDGE_INTEL_COMMON_HPET_H + +#include <types.h> + +void set_global_reset(const bool enable); + +#endif /* SOUTHBRIDGE_INTEL_COMMON_HPET_H */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 34ae2f112a..18f77703a4 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -21,6 +21,7 @@ config SOUTH_BRIDGE_OPTIONS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_ME select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC |