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-rw-r--r--src/mainboard/google/cherry/mainboard.c2
-rw-r--r--src/mainboard/google/cherry/romstage.c2
-rw-r--r--src/soc/mediatek/common/rtc_mt6359p.c (renamed from src/soc/mediatek/mt8192/rtc.c)0
-rw-r--r--src/soc/mediatek/mt8192/Makefile.inc4
-rw-r--r--src/soc/mediatek/mt8195/Makefile.inc2
-rw-r--r--src/soc/mediatek/mt8195/include/soc/pll.h1
-rw-r--r--src/soc/mediatek/mt8195/include/soc/rtc.h218
-rw-r--r--src/soc/mediatek/mt8195/include/soc/usb.h24
-rw-r--r--src/soc/mediatek/mt8195/usb.c12
9 files changed, 263 insertions, 2 deletions
diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c
index 37d3d1c6e2..5015531d9a 100644
--- a/src/mainboard/google/cherry/mainboard.c
+++ b/src/mainboard/google/cherry/mainboard.c
@@ -10,6 +10,7 @@
#include <soc/i2c.h>
#include <soc/mt6360.h>
#include <soc/regulator.h>
+#include <soc/usb.h>
DEFINE_BITFIELD(MSDC0_DRV, 29, 0)
DEFINE_BITFIELD(MSDC1_DRV, 17, 0)
@@ -105,6 +106,7 @@ static void mainboard_init(struct device *dev)
{
configure_emmc();
configure_sdcard();
+ setup_usb_host();
}
static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c
index f4bb1ca27b..cdb2681240 100644
--- a/src/mainboard/google/cherry/romstage.c
+++ b/src/mainboard/google/cherry/romstage.c
@@ -5,6 +5,7 @@
#include <soc/mt6315.h>
#include <soc/mt6359p.h>
#include <soc/pmif.h>
+#include <soc/rtc.h>
void platform_romstage_main(void)
{
@@ -12,4 +13,5 @@ void platform_romstage_main(void)
mt6359p_init();
mt6315_init();
clk_buf_init();
+ rtc_boot();
}
diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/common/rtc_mt6359p.c
index b5c381b50d..b5c381b50d 100644
--- a/src/soc/mediatek/mt8192/rtc.c
+++ b/src/soc/mediatek/common/rtc_mt6359p.c
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 484cfb8e21..24394173d9 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -38,7 +38,7 @@ romstage-y += ../common/uart.c
romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
romstage-y += ../common/pmif_spi.c pmif_spi.c
romstage-y += ../common/pmif_spmi.c pmif_spmi.c
-romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
+romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c
@@ -57,7 +57,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += ../common/pmif.c
-ramstage-y += ../common/rtc.c rtc.c
+ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
ramstage-y += soc.c
ramstage-y += spm.c
ramstage-y += sspm.c
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index cc855b2b81..514acbdfe8 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -35,6 +35,7 @@ romstage-y += ../common/pmif_spi.c pmif_spi.c
romstage-y += ../common/pmif_spmi.c pmif_spmi.c
romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c
+romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
@@ -46,6 +47,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c
ramstage-y += ../common/timer.c timer.c
ramstage-y += ../common/uart.c
+ramstage-y += ../common/usb.c usb.c
ramstage-y += ../common/wdt.c
ramstage-y += mt6360.c
diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h
index 60fcbd9884..cc133c8b14 100644
--- a/src/soc/mediatek/mt8195/include/soc/pll.h
+++ b/src/soc/mediatek/mt8195/include/soc/pll.h
@@ -168,6 +168,7 @@ struct mtk_topckgen_regs {
};
check_member(mtk_topckgen_regs, clk_cfg_0, 0x0020);
+check_member(mtk_topckgen_regs, clk_cfg_11_clr, 0x00ac);
check_member(mtk_topckgen_regs, clk_extck_reg, 0x0204);
check_member(mtk_topckgen_regs, clk26cali_0, 0x0218);
check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x022c);
diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h
new file mode 100644
index 0000000000..908473166e
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/rtc.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_RTC_H
+#define SOC_MEDIATEK_MT8195_RTC_H
+
+#include <soc/pmif.h>
+#include <stdbool.h>
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0x0588,
+ RTC_IRQ_STA = 0x058A,
+ RTC_IRQ_EN = 0x058C,
+ RTC_CII_EN = 0x058E,
+};
+
+enum {
+ RTC_TC_SEC = 0x0592,
+ RTC_TC_MIN = 0x0594,
+ RTC_TC_HOU = 0x0596,
+ RTC_TC_DOM = 0x0598,
+ RTC_TC_DOW = 0x059A,
+ RTC_TC_MTH = 0x059C,
+ RTC_TC_YEA = 0x059E,
+};
+
+enum {
+ RTC_AL_SEC = 0x05A0,
+ RTC_AL_MIN = 0x05A2,
+ RTC_AL_HOU = 0x05A4,
+ RTC_AL_DOM = 0x05A6,
+ RTC_AL_DOW = 0x05A8,
+ RTC_AL_MTH = 0x05AA,
+ RTC_AL_YEA = 0x05AC,
+ RTC_AL_MASK = 0x0590,
+};
+
+enum {
+ RTC_OSC32CON = 0x05AE,
+ RTC_CON = 0x05C4,
+ RTC_WRTGR = 0x05C2,
+};
+
+enum {
+ RTC_POWERKEY1 = 0x05B0,
+ RTC_POWERKEY2 = 0x05B2,
+};
+
+enum {
+ RTC_PDN1 = 0x05B4,
+ RTC_PDN2 = 0x05B6,
+ RTC_SPAR0 = 0x05B8,
+ RTC_SPAR1 = 0x05BA,
+ RTC_PROT = 0x05BC,
+ RTC_DIFF = 0x05BE,
+ RTC_CALI = 0x05C0,
+};
+
+enum {
+ RTC_BBPU_ENABLE_ALARM = 1U << 0,
+ RTC_BBPU_SPAR_SW = 1U << 1,
+ RTC_BBPU_RESET_SPAR = 1U << 2,
+ RTC_BBPU_RESET_ALARM = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6,
+ RTC_CBUSY_TIMEOUT_US = 1000000,
+};
+
+enum {
+ RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
+ RTC_CON_EOSC32_LPEN = 1U << 1,
+ RTC_CON_XOSC32_LPEN = 1U << 2,
+ RTC_CON_LPRST = 1U << 3,
+ RTC_CON_CDBO = 1U << 4,
+ RTC_CON_F32KOB = 1U << 5,
+ RTC_CON_GPO = 1U << 6,
+ RTC_CON_GOE = 1U << 7,
+ RTC_CON_GSR = 1U << 8,
+ RTC_CON_GSMT = 1U << 9,
+ RTC_CON_GPEN = 1U << 10,
+ RTC_CON_GPU = 1U << 11,
+ RTC_CON_GE4 = 1U << 12,
+ RTC_CON_GE8 = 1U << 13,
+ RTC_CON_GPI = 1U << 14,
+ RTC_CON_LPSTA_RAW = 1U << 15,
+};
+
+enum {
+ RTC_XOSCCALI_MASK = 0x1F << 0,
+ RTC_XOSC32_ENB = 1U << 5,
+ RTC_EMB_HW_MODE = 0U << 6,
+ RTC_EMB_K_EOSC32_MODE = 1U << 6,
+ RTC_EMB_SW_DCXO_MODE = 2U << 6,
+ RTC_EMB_SW_EOSC32_MODE = 3U << 6,
+ RTC_EMBCK_SEL_MODE_MASK = 3U << 6,
+ RTC_EMBCK_SRC_SEL = 1U << 8,
+ RTC_EMBCK_SEL_OPTION = 1U << 9,
+ RTC_GPS_CKOUT_EN = 1U << 10,
+ RTC_EOSC32_VCT_EN = 1U << 11,
+ RTC_EOSC32_CHOP_EN = 1U << 12,
+ RTC_GP_OSC32_CON = 2U << 13,
+ RTC_REG_XOSC32_ENB = 1U << 15,
+};
+
+enum {
+ OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
+ RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
+ RTC_EMB_K_EOSC32_MODE,
+};
+
+enum {
+ RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
+ RTC_LPD_OPT_EOSC_LPD = 1U << 13,
+ RTC_LPD_OPT_XOSC_LPD = 2U << 13,
+ RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
+ RTC_LPD_OPT_MASK = 3U << 13,
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_SCK_TOP_CON0 = 0x050C,
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
+ PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
+ PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
+ PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+ PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+ PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+ PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+ PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+ PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C,
+};
+
+enum {
+ PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
+ PMIC_RG_FQMTR_CK_PDN_SHIFT = 11,
+};
+
+enum {
+ PMIC_RG_BANK_FQMTR_RST = 0x522,
+};
+
+enum {
+ PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
+ PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
+};
+
+/* PMIC Frequency Meter Definition */
+enum {
+ PMIC_RG_FQMTR_CKSEL = 0x0118,
+ PMIC_RG_FQMTR_RST = 0x013A,
+ PMIC_RG_FQMTR_CON0 = 0x0546,
+ PMIC_RG_FQMTR_WINSET = 0x0548,
+ PMIC_RG_FQMTR_DATA = 0x054A,
+ FQMTR_TIMEOUT_US = 8000,
+};
+
+enum {
+ PMIC_FQMTR_FIX_CLK_26M = 0U << 0,
+ PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0,
+ PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0,
+ PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0,
+ PMIC_FQMTR_FIX_CLK_DCXO1M_CK = 4U << 0,
+ PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0,
+ PMIC_FQMTR_FIX_CLK_PMU_32K = 6U << 0,
+ PMIC_FQMTR_CKSEL_MASK = 7U << 0,
+};
+
+enum {
+ PMIC_FQMTR_RST_SHIFT = 8,
+};
+
+enum {
+ PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0,
+ PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0,
+ PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0,
+ PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
+ PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0,
+ PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0,
+ PMIC_FQMTR_CON0_TEST_CK = 6U << 0,
+ PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0,
+ PMIC_FQMTR_CON0_BUSY = 1U << 3,
+ PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4,
+ PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15,
+};
+
+enum {
+ RTC_FQMTR_LOW_BASE = 794 - 2,
+ RTC_FQMTR_HIGH_BASE = 794 + 2,
+};
+
+enum {
+ RTC_XOSCCALI_START = 0x00,
+ RTC_XOSCCALI_END = 0x1f,
+};
+
+enum {
+ RTC_TC_MTH_MASK = 0xf,
+};
+
+enum {
+ RTC_K_EOSC_RSV_0 = 1 << 8,
+ RTC_K_EOSC_RSV_1 = 1 << 9,
+ RTC_K_EOSC_RSV_2 = 1 << 10,
+};
+
+void rtc_read(u16 addr, u16 *rdata);
+void rtc_write(u16 addr, u16 wdata);
+void rtc_bbpu_power_on(void);
+int rtc_init(int recover);
+bool rtc_gpio_init(void);
+void rtc_boot(void);
+u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
+#endif /* SOC_MEDIATEK_MT8195_RTC_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h
new file mode 100644
index 0000000000..e39ec3841d
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/usb.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_USB_H
+#define SOC_MEDIATEK_MT8195_USB_H
+
+#include <soc/usb_common.h>
+
+struct ssusb_sif_port {
+ struct sif_u2_phy_com u2phy;
+ u32 reserved0[64 * 5];
+ struct sif_u3phyd u3phyd;
+ u32 reserved1[64];
+ struct sif_u3phya u3phya;
+ struct sif_u3phya_da u3phya_da;
+ u32 reserved2[64 * 3];
+};
+check_member(ssusb_sif_port, u3phyd, 0x600);
+check_member(ssusb_sif_port, u3phya, 0x800);
+check_member(ssusb_sif_port, u3phya_da, 0x900);
+check_member(ssusb_sif_port, reserved2, 0xa00);
+
+#define USB_PORT_NUMBER 1
+
+#endif
diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c
new file mode 100644
index 0000000000..7b6347e605
--- /dev/null
+++ b/src/soc/mediatek/mt8195/usb.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/infracfg.h>
+#include <soc/pll.h>
+#include <soc/usb.h>
+
+void mtk_usb_prepare(void)
+{
+ setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15));
+ setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31));
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 20:26:25 +0000