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-rw-r--r--src/mainboard/amd/onyx_poc/devicetree.cb24
-rw-r--r--src/soc/amd/genoa_poc/chipset.cb160
-rw-r--r--src/vendorcode/amd/opensil/Kconfig9
-rw-r--r--src/vendorcode/amd/opensil/chip/mpio/chip.h8
-rw-r--r--src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c6
-rw-r--r--src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h2
-rw-r--r--src/vendorcode/amd/opensil/stub/mpio/chip.c2
-rw-r--r--src/vendorcode/amd/opensil/stub/mpio/chip.h2
8 files changed, 115 insertions, 98 deletions
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb
index c1b2f5c28c..f3c0be4561 100644
--- a/src/mainboard/amd/onyx_poc/devicetree.cb
+++ b/src/mainboard/amd/onyx_poc/devicetree.cb
@@ -55,7 +55,7 @@ chip soc/amd/genoa_poc
device domain 0 on
device ref iommu_0 on end
device ref rcec_0 on end
- chip vendorcode/amd/opensil/genoa_poc/mpio # P2
+ chip vendorcode/amd/opensil/chip/mpio # P2
register "type" = "IFTYPE_PCIE"
register "start_lane" = "48"
register "end_lane" = "63"
@@ -63,7 +63,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_0_0_a on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio # G2
+ chip vendorcode/amd/opensil/chip/mpio # G2
register "type" = "IFTYPE_PCIE"
register "start_lane" = "112"
register "end_lane" = "127"
@@ -72,7 +72,7 @@ chip soc/amd/genoa_poc
register "hotplug" = "ServerExpress"
device ref gpp_bridge_0_0_b on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "128"
register "end_lane" = "131"
@@ -93,7 +93,7 @@ chip soc/amd/genoa_poc
device domain 1 on
device ref iommu_1 on end
device ref rcec_1 on end
- chip vendorcode/amd/opensil/genoa_poc/mpio # P3
+ chip vendorcode/amd/opensil/chip/mpio # P3
register "type" = "IFTYPE_PCIE"
register "start_lane" = "16"
register "end_lane" = "31"
@@ -101,7 +101,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_1_0_a on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio # G3
+ chip vendorcode/amd/opensil/chip/mpio # G3
register "type" = "IFTYPE_PCIE"
register "start_lane" = "80"
register "end_lane" = "95"
@@ -114,7 +114,7 @@ chip soc/amd/genoa_poc
device domain 2 on
device ref iommu_2 on end
device ref rcec_2 on end
- chip vendorcode/amd/opensil/genoa_poc/mpio # P1
+ chip vendorcode/amd/opensil/chip/mpio # P1
register "type" = "IFTYPE_PCIE"
register "start_lane" = "32"
register "end_lane" = "47"
@@ -123,7 +123,7 @@ chip soc/amd/genoa_poc
register "hotplug" = "ServerExpress"
device ref gpp_bridge_2_0_a on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio # G1
+ chip vendorcode/amd/opensil/chip/mpio # G1
register "type" = "IFTYPE_PCIE"
register "start_lane" = "64"
register "end_lane" = "79"
@@ -137,7 +137,7 @@ chip soc/amd/genoa_poc
device domain 3 on
device ref iommu_3 on end
device ref rcec_3 on end
- chip vendorcode/amd/opensil/genoa_poc/mpio # P0
+ chip vendorcode/amd/opensil/chip/mpio # P0
register "type" = "IFTYPE_PCIE"
register "start_lane" = "0"
register "end_lane" = "15"
@@ -145,7 +145,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_a on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio # G0
+ chip vendorcode/amd/opensil/chip/mpio # G0
register "type" = "IFTYPE_PCIE"
register "start_lane" = "96"
register "end_lane" = "111"
@@ -153,7 +153,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_b on end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "132"
register "end_lane" = "133"
@@ -161,7 +161,7 @@ chip soc/amd/genoa_poc
register "aspm" = "L1"
device ref gpp_bridge_3_0_c on end # WAFL
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "134"
register "end_lane" = "134"
@@ -170,7 +170,7 @@ chip soc/amd/genoa_poc
register "bmc" = "1"
device ref gpp_bridge_3_1_c on end # BMC
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
register "type" = "IFTYPE_PCIE"
register "start_lane" = "135"
register "end_lane" = "135"
diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb
index 92dcb5df96..832b9b6f4a 100644
--- a/src/soc/amd/genoa_poc/chipset.cb
+++ b/src/soc/amd/genoa_poc/chipset.cb
@@ -16,78 +16,78 @@ chip soc/amd/genoa_poc
device pci 00.3 alias rcec_0 off end
device pci 01.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.1 alias gpp_bridge_0_0_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.2 alias gpp_bridge_0_1_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.3 alias gpp_bridge_0_2_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.4 alias gpp_bridge_0_3_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.5 alias gpp_bridge_0_4_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.6 alias gpp_bridge_0_5_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.7 alias gpp_bridge_0_6_a off end
end
device pci 02.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.1 alias gpp_bridge_0_7_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.2 alias gpp_bridge_0_8_a off end
end
device pci 03.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.1 alias gpp_bridge_0_0_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.2 alias gpp_bridge_0_1_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.3 alias gpp_bridge_0_2_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.4 alias gpp_bridge_0_3_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.5 alias gpp_bridge_0_4_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.6 alias gpp_bridge_0_5_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.7 alias gpp_bridge_0_6_b off end
end
device pci 04.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.1 alias gpp_bridge_0_7_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.2 alias gpp_bridge_0_8_b off end
end
device pci 05.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.1 alias gpp_bridge_0_0_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.2 alias gpp_bridge_0_1_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.3 alias gpp_bridge_0_2_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.4 alias gpp_bridge_0_3_c off end
end
@@ -128,64 +128,64 @@ chip soc/amd/genoa_poc
device pci 00.3 alias rcec_1 off end
device pci 01.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.1 alias gpp_bridge_1_0_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.2 alias gpp_bridge_1_1_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.3 alias gpp_bridge_1_2_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.4 alias gpp_bridge_1_3_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.5 alias gpp_bridge_1_4_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.6 alias gpp_bridge_1_5_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.7 alias gpp_bridge_1_6_a off end
end
device pci 02.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.1 alias gpp_bridge_1_7_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.2 alias gpp_bridge_1_8_a off end
end
device pci 03.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.1 alias gpp_bridge_1_0_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.2 alias gpp_bridge_1_1_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.3 alias gpp_bridge_1_2_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.4 alias gpp_bridge_1_3_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.5 alias gpp_bridge_1_4_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.6 alias gpp_bridge_1_5_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.7 alias gpp_bridge_1_6_b off end
end
device pci 04.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.1 alias gpp_bridge_1_7_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.2 alias gpp_bridge_1_8_b off end
end
@@ -207,64 +207,64 @@ chip soc/amd/genoa_poc
device pci 00.3 alias rcec_2 off end
device pci 01.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.1 alias gpp_bridge_2_0_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.2 alias gpp_bridge_2_1_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.3 alias gpp_bridge_2_2_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.4 alias gpp_bridge_2_3_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.5 alias gpp_bridge_2_4_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.6 alias gpp_bridge_2_5_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.7 alias gpp_bridge_2_6_a off end
end
device pci 02.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.1 alias gpp_bridge_2_7_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.2 alias gpp_bridge_2_8_a off end
end
device pci 03.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.1 alias gpp_bridge_2_0_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.2 alias gpp_bridge_2_1_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.3 alias gpp_bridge_2_2_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.4 alias gpp_bridge_2_3_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.5 alias gpp_bridge_2_4_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.6 alias gpp_bridge_2_5_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.7 alias gpp_bridge_2_6_b off end
end
device pci 04.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.1 alias gpp_bridge_2_7_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.2 alias gpp_bridge_2_8_b off end
end
@@ -286,78 +286,78 @@ chip soc/amd/genoa_poc
device pci 00.3 alias rcec_3 off end
device pci 01.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.1 alias gpp_bridge_3_0_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.2 alias gpp_bridge_3_1_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.3 alias gpp_bridge_3_2_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.4 alias gpp_bridge_3_3_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.5 alias gpp_bridge_3_4_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.6 alias gpp_bridge_3_5_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 01.7 alias gpp_bridge_3_6_a off end
end
device pci 02.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.1 alias gpp_bridge_3_7_a off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 02.2 alias gpp_bridge_3_8_a off end
end
device pci 03.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.1 alias gpp_bridge_3_0_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.2 alias gpp_bridge_3_1_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.3 alias gpp_bridge_3_2_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.4 alias gpp_bridge_3_3_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.5 alias gpp_bridge_3_4_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.6 alias gpp_bridge_3_5_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 03.7 alias gpp_bridge_3_6_b off end
end
device pci 04.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.1 alias gpp_bridge_3_7_b off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 04.2 alias gpp_bridge_3_8_b off end
end
device pci 05.0 on end # Dummy device function, do not disable
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.1 alias gpp_bridge_3_0_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.2 alias gpp_bridge_3_1_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.3 alias gpp_bridge_3_2_c off end
end
- chip vendorcode/amd/opensil/genoa_poc/mpio
+ chip vendorcode/amd/opensil/chip/mpio
device pci 05.4 alias gpp_bridge_3_3_c off end
end
diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig
index 00f373f142..3daae5071d 100644
--- a/src/vendorcode/amd/opensil/Kconfig
+++ b/src/vendorcode/amd/opensil/Kconfig
@@ -23,4 +23,13 @@ config AMD_OPENSIL_PATH
Set to the path of the openSIL directory containing meson.build.
example
+config AMD_OPENSIL_MPIO_CHIP_H_FILE
+ string "Location of specific MPIO chip.h implementation"
+ default "../../genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC
+ default "../../stub/mpio/chip.h"
+ help
+ Set to the location of the MPIO chip.h in the selected openSIL
+ implementation, so that the common MPIO chip.h file can include the
+ specific one.
+
endif
diff --git a/src/vendorcode/amd/opensil/chip/mpio/chip.h b/src/vendorcode/amd/opensil/chip/mpio/chip.h
new file mode 100644
index 0000000000..812df6b6d4
--- /dev/null
+++ b/src/vendorcode/amd/opensil/chip/mpio/chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef OPENSIL_MPIO_CHIP_H
+#define OPENSIL_MPIO_CHIP_H
+
+#include CONFIG_AMD_OPENSIL_MPIO_CHIP_H_FILE
+
+#endif /* OPENSIL_MPIO_CHIP_H */
diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
index 089096f8c4..609ac5516d 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
+++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
@@ -9,7 +9,7 @@
#include "chip.h"
#include "../opensil.h"
-struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = {
+struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
.name = "AMD GENOA MPIO",
};
@@ -130,7 +130,7 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev
static uint32_t slot_num;
const uint32_t domain = dev->upstream->dev->path.domain.domain;
const uint32_t devfn = dev->path.pci.devfn;
- const struct vendorcode_amd_opensil_genoa_poc_mpio_config *const config = dev->chip_info;
+ const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info;
printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n",
domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
@@ -199,7 +199,7 @@ void configure_mpio(void)
/* Find all devices with this chip that are directly below the chip */
for (struct device *dev = &dev_root; dev; dev = dev->next)
- if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops &&
+ if (dev->chip_ops == &vendorcode_amd_opensil_chip_mpio_ops &&
dev->chip_info != dev->upstream->dev->chip_info)
per_device_config(mpio_data, dev);
}
diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
index 36d6bafce8..9b4d226b49 100644
--- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
+++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
@@ -54,7 +54,7 @@ enum pcie_aspm {
L0sL1,
};
-struct vendorcode_amd_opensil_genoa_poc_mpio_config {
+struct vendorcode_amd_opensil_chip_mpio_config {
enum mpio_type type;
uint8_t start_lane;
uint8_t end_lane;
diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.c b/src/vendorcode/amd/opensil/stub/mpio/chip.c
index 895814ded3..9b515b3257 100644
--- a/src/vendorcode/amd/opensil/stub/mpio/chip.c
+++ b/src/vendorcode/amd/opensil/stub/mpio/chip.c
@@ -3,6 +3,6 @@
#include <device/device.h>
#include "chip.h"
-struct chip_operations vendorcode_amd_opensil_stub_mpio_ops = {
+struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = {
.name = "AMD openSIL stub MPIO",
};
diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h
index 0957ff0213..456463336b 100644
--- a/src/vendorcode/amd/opensil/stub/mpio/chip.h
+++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h
@@ -60,7 +60,7 @@ enum pcie_slot_power_limit_scale {
SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */
};
-struct vendorcode_amd_opensil_stub_mpio_config {
+struct vendorcode_amd_opensil_chip_mpio_config {
enum mpio_engine_type type;
uint8_t start_lane;
uint8_t end_lane;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 00:59:20 +0000