diff options
Diffstat (limited to 'src')
24 files changed, 6 insertions, 24 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 937986e406..d4ab530720 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -46,7 +46,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 36a73b5316..fae925fcf9 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "PchHdaVcType" = "Vc1" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index a6689e5976..862166320e 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 3c33b8ca71..5e927b4a36 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 888e111c46..ac3ee8b77e 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -70,7 +70,6 @@ chip soc/intel/skylake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 1dd8dbc9dc..1e1b8e8722 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index fafd0c1ac1..432ef99d5c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -45,7 +45,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 7c5c33278b..2dc0703566 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 19a8cf721e..8e1f954d8a 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index dc133b6954..0a67d4d7f9 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index cc72e7730f..8959a2902e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ada2be83e8..54faf473f8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -45,7 +45,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index b0ddef6801..777c5214c7 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -35,7 +35,6 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 0262498623..0b1ba1d9bc 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -157,7 +157,7 @@ chip soc/intel/skylake device pci 1f.0 on end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 off end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b7b569d7cc..cfb50e3e20 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -1,7 +1,6 @@ chip soc/intel/skylake # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "0" @@ -126,6 +125,7 @@ chip soc/intel/skylake device pci 1e.3 on end # GSPI #1 device pci 1e.4 off end # eMMC device pci 1e.6 off end # SDCard + device pci 1f.3 on end # Intel HDA device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index a269d01458..5cfb10da50 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -7,7 +7,6 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0201" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "HeciEnabled" = "0" @@ -134,5 +133,6 @@ chip soc/intel/skylake device pnp 0c31.0 on end end end # LPC Interface + device pci 1f.3 on end # Intel HDA end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 283c0a1f20..aebda8567c 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -24,7 +24,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index a8066d5cb2..2a0558e190 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -18,7 +18,6 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" # FSP Configuration - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 578abf0795..a58e169b8c 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "SataPortsDevSlp[1]" = "0" register "SataPortsDevSlp[2]" = "0" register "SataSpeedLimit" = "2" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d66a38c145..9071a7b377 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index a181352466..5aa51d3e06 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 1efb399799..01aec8b948 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a73aa8daab..562d791a6d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -272,7 +272,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) dev = pcidev_path_on_root(PCH_DEVFN_ISH); params->PchIshEnable = dev ? dev->enabled : 0; - params->PchHdaEnable = config->EnableAzalia; + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 3f55c18b8b..fc86cfd58f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -157,7 +157,6 @@ struct soc_intel_skylake_config { u8 SataSpeedLimit; /* Audio related */ - u8 EnableAzalia; u8 DspEnable; /* HDA Virtual Channel Type Select */ |