diff options
Diffstat (limited to 'src')
21 files changed, 26 insertions, 127 deletions
diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl new file mode 100644 index 0000000000..73d626fbea --- /dev/null +++ b/src/acpi/acpigen_extern.asl @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we provide it runtime via NVBx and NVSx variables from acpigen. + */ + +#if CONFIG(ACPI_SOC_NVS) +External (NVB0, IntObj) +External (NVS0, IntObj) +OperationRegion (GNVS, SystemMemory, NVB0, NVS0) +#endif + +#if CONFIG(ACPI_HAS_DEVICE_NVS) +External (NVB1, IntObj) +External (NVS1, IntObj) +OperationRegion (DNVS, SystemMemory, NVB1, NVS1) +#endif diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index 853b0877b3..761c1b541d 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -1 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen_extern.asl> diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 18c1b33130..010b0e0149 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -71,12 +71,14 @@ void acpi_fill_gnvs(void) mainboard_fill_gnvs(gnvs); acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); + acpigen_write_name_dword("NVB0", (uintptr_t)gnvs); + acpigen_write_name_dword("NVS0", CONFIG(MAINBOARD_HAS_CHROMEOS) ? 0x1000 : 0x100); acpigen_pop_len(); if (CONFIG(ACPI_HAS_DEVICE_NVS)) { acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSD", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET); + acpigen_write_name_dword("NVB1", (uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET); + acpigen_write_name_dword("NVS1", 0x1000); acpigen_pop_len(); } } diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 1c19059425..4b0e774755 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -9,9 +9,6 @@ Name (PICM, Zero) /* Interrupt Mode used by OS. Assume PIC. */ * */ -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 8bfc7b2b80..252ceda911 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -6,9 +6,6 @@ * */ -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 97677ad02e..07853defe3 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -6,9 +6,6 @@ * */ -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl index aa0e9533f8..d570788985 100644 --- a/src/soc/intel/baytrail/acpi/device_nvs.asl +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -External (NVSD) - -OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) Field (DNVS, ByteAcc, NoLock, Preserve) { /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 293daa94a3..eb51cada51 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -4,16 +4,6 @@ Name(\PICM, 0) /* IOAPIC/8259 */ -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index aa0e9533f8..d570788985 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -External (NVSD) - -OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) Field (DNVS, ByteAcc, NoLock, Preserve) { /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 6aa595713b..628a79190a 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -4,16 +4,6 @@ Name(\PICM, 0) /* IOAPIC/8259 */ -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl index 30bb5b5cd0..fb95df8e6e 100644 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -External (NVSD) - -OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) Field (DNVS, ByteAcc, NoLock, Preserve) { /* Device enables in ACPI mode */ diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 88fe4b1218..60d5737165 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -4,15 +4,6 @@ Name (\PICM, 0) // IOAPIC/8259 -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 6a6970f0a0..d508544cb0 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -4,16 +4,6 @@ Name (\PICM, 0) // IOAPIC/8259 -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 97fa02f4a2..659129f550 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -4,15 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 928c5e6eac..45c784e18d 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -4,16 +4,6 @@ Name (\PICM, 0) // IOAPIC/8259 -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 23b6769bed..eafa3adacc 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -4,14 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 8bd222fbc1..dfd5a560c8 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -4,14 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 021de14e2c..24efba67f8 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -4,14 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 3d0d3b2790..d2af885b0e 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -4,14 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 174d12f3c7..51f6935c87 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -4,14 +4,6 @@ Name(\PICM, 0) // IOAPIC/8259 -/* Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 758667d02d..179a9912cc 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -4,15 +4,6 @@ Name (\PICM, 0) // IOAPIC/8259 -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ |