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-rw-r--r--src/cpu/amd/pi/00630F01/Kconfig69
-rw-r--r--src/cpu/amd/pi/00630F01/Makefile.inc35
-rw-r--r--src/cpu/amd/pi/00630F01/acpi/cpu.asl111
-rw-r--r--src/cpu/amd/pi/00630F01/chip_name.c24
-rw-r--r--src/cpu/amd/pi/00630F01/fixme.c91
-rw-r--r--src/cpu/amd/pi/00630F01/model_15_init.c147
-rw-r--r--src/cpu/amd/pi/00630F01/udelay.c45
-rw-r--r--src/cpu/amd/pi/Kconfig2
-rw-r--r--src/cpu/amd/pi/Makefile.inc1
-rw-r--r--src/cpu/amd/pi/heapmanager.c4
10 files changed, 527 insertions, 2 deletions
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
new file mode 100644
index 0000000000..4c578d488d
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/Kconfig
@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config CPU_AMD_PI_00630F01
+ bool
+ select PCI_IO_CFG_EXT
+ select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_PI_00630F01
+
+config CPU_ADDR_BITS
+ int
+ default 48
+
+config CPU_SOCKET_TYPE
+ hex
+ default 0x10
+
+# DDR2 and REG
+config DIMM_SUPPORT
+ hex
+ default 0x0104
+
+config EXT_RT_TBL_SUPPORT
+ bool
+ default n
+
+config EXT_CONF_SUPPORT
+ bool
+ default n
+
+config CBB
+ hex
+ default 0x0
+
+config CDB
+ hex
+ default 0x18
+
+config XIP_ROM_BASE
+ hex
+ default 0xfff80000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x100000
+
+config HIGH_SCRATCH_MEMORY_SIZE
+ hex
+ # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
+ default 0x71000
+
+endif
diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
new file mode 100644
index 0000000000..b08877ff40
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/Makefile.inc
@@ -0,0 +1,35 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += fixme.c
+
+ramstage-y += fixme.c
+ramstage-y += chip_name.c
+ramstage-y += model_15_init.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../smm
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
new file mode 100644
index 0000000000..c15e58cb5f
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique core number for this processor within a socket */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P008, /* name space name */
+ 8, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P009, /* name space name */
+ 9, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P010, /* name space name */
+ 10, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P011, /* name space name */
+ 11, /* Unique core number for this processor within a socket */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ } /* End _PR scope */
+
diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c
new file mode 100644
index 0000000000..fa2941af33
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/chip_name.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations cpu_amd_pi_00630F01_ops = {
+ CHIP_NAME("AMD CPU Family 15h Model 30")
+};
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
new file mode 100644
index 0000000000..f032f02fdb
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include "amdlib.h"
+
+void amd_initcpuio(void)
+{
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
+ PciData |= 1 << 7; /* set NP (non-posted) bit */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; /* last address before non-posted range */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+}
+
+void amd_initmmio(void)
+{
+ UINT64 MsrReg;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+}
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
new file mode 100644
index 0000000000..324908136c
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/acpi.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <cpu/amd/pi/s3_resume.h>
+#endif
+
+static void model_15_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Model 15 Init.\n");
+
+ u8 i;
+ msr_t msr;
+ int msrno;
+ unsigned int cpu_idx;
+#if CONFIG_LOGICAL_CPUS
+ u32 siblings;
+#endif
+
+ disable_cache ();
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+ // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
+ msr.lo = msr.hi = 0;
+ wrmsr (0x259, msr);
+ msr.lo = msr.hi = 0x1e1e1e1e;
+ wrmsr(0x250, msr);
+ wrmsr(0x258, msr);
+ for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr (msrno, msr);
+
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3)
+ restore_mtrr();
+#endif
+
+ x86_mtrr_check();
+ x86_enable_cache();
+
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < 6; i++) {
+ wrmsr(MCI_STATUS + (i * 4), msr);
+ }
+
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS
+ siblings = cpuid_ecx(0x80000008) & 0xff;
+
+ if (siblings > 0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1 << (33 - 32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+ /* DisableCf8ExtCfg */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.hi &= ~(1 << (46 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ cpu_idx = cpu_info()->index;
+ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
+
+ /* Set SMM base address for this CPU */
+ msr = rdmsr(MSR_SMM_BASE);
+ msr.lo = SMM_BASE - (cpu_idx * 0x400);
+ wrmsr(MSR_SMM_BASE, msr);
+
+ /* Enable the SMM memory window */
+ msr = rdmsr(MSR_SMM_MASK);
+ msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
+ wrmsr(MSR_SMM_MASK, msr);
+ }
+
+ /* Write protect SMM space with SMMLOCK. */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_15_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x630f00 }, /* KV-A0 */
+ { X86_VENDOR_AMD, 0x630f01 }, /* KV-A1 */
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_15 __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c
new file mode 100644
index 0000000000..5873237b0c
--- /dev/null
+++ b/src/cpu/amd/pi/00630F01/udelay.c
@@ -0,0 +1,45 @@
+/*
+ * udelay() impementation for SMI handlers
+ * This is neat in that it never writes to hardware registers, and thus does not
+ * modify the state of the hardware while servicing SMIs.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <delay.h>
+#include <stdint.h>
+
+void udelay(uint32_t us)
+{
+ uint8_t fid, did, pstate_idx;
+ uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
+ msr_t msr;
+ const uint64_t tsc_base = 100000000;
+
+ /* Get initial timestamp before we do the math */
+ tsc_start = rdtscll();
+
+ /* Get the P-state. This determines which MSR to read */
+ msr = rdmsr(0xc0010063);
+ pstate_idx = msr.lo & 0x07;
+
+ /* Get FID and VID for current P-State */
+ msr = rdmsr(0xc0010064 + pstate_idx);
+
+ /* Extract the FID and VID values */
+ fid = msr.lo & 0x3f;
+ did = (msr.lo >> 6) & 0x7;
+
+ /* Calculate the CPU clock (from base freq of 100MHz) */
+ tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
+
+ /* Now go on and wait */
+ tsc_wait_ticks = (tsc_clock / 1000000) * us;
+
+ do {
+ tsc_now = rdtscll();
+ } while (tsc_now - tsc_wait_ticks < tsc_start);
+}
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 88c4745754..3fa62636fa 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -19,6 +19,7 @@
config CPU_AMD_PI
bool
+ default y if CPU_AMD_PI_00630F01
default y if CPU_AMD_PI_00730F01
default n
select ARCH_BOOTBLOCK_X86_32
@@ -74,4 +75,5 @@ config S3_DATA_SIZE
endif # CPU_AMD_PI
+source src/cpu/amd/pi/00630F01/Kconfig
source src/cpu/amd/pi/00730F01/Kconfig
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 8228b12182..4909e3e95f 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -17,6 +17,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
romstage-y += s3_resume.c
diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c
index aa251e07a4..22c72fb941 100644
--- a/src/cpu/amd/pi/heapmanager.c
+++ b/src/cpu/amd/pi/heapmanager.c
@@ -28,7 +28,7 @@ void EmptyHeap(void)
memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
}
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01)
#define AGESA_RUNTIME_SIZE 4096
@@ -74,7 +74,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
AllocParams->BufferPointer = NULL;
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01)
/* if the allocation is for runtime use simple CBMEM data */
if (Data == HEAP_CALLOUT_RUNTIME)
return alloc_cbmem(AllocParams);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 19:39:40 +0000