diff options
Diffstat (limited to 'src')
23 files changed, 65 insertions, 90 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index bca9f71f19..c7d8722829 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -15,12 +15,12 @@ #include <arch/acpi.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <fsp/memmap.h> #include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ -#include <reset.h> #include <string.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> @@ -164,7 +164,8 @@ void raminit(struct romstage_params *params) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); #endif } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 8e8c24c96c..e1910e6ad5 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -22,6 +22,7 @@ #include <assert.h> #include <console/console.h> #include <cbmem.h> +#include <cf9_reset.h> #include <cpu/intel/microcode.h> #include <cpu/x86/mtrr.h> #include <ec/google/chromeec/ec.h> @@ -29,7 +30,6 @@ #include <elog.h> #include <fsp/romstage.h> #include <mrc_cache.h> -#include <reset.h> #include <program_loading.h> #include <romstage_handoff.h> #include <smbios.h> @@ -134,7 +134,8 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } @@ -164,7 +165,8 @@ void romstage_common(struct romstage_params *params) /* Create romstage handof information */ if (romstage_handoff_init( params->power_state->prev_sleep_state == ACPI_S3) < 0) - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } void after_cache_as_ram_stage(void) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1026c7982d..5eeea29504 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -18,6 +18,7 @@ #include <assert.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <elog.h> #include <fsp/api.h> @@ -25,7 +26,6 @@ #include <memrange.h> #include <mrc_cache.h> #include <program_loading.h> -#include <reset.h> #include <romstage_handoff.h> #include <string.h> #include <symbols.h> @@ -80,7 +80,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); } } @@ -214,7 +215,8 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, * returning error. Invoking a reset here saves time. */ if (!arch_upd->NvsBufferPtr) - hard_reset(); + /* FIXME: A "system" reset is likely enough: */ + full_reset(); arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME; } else { if (arch_upd->NvsBufferPtr) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index f84d69cec5..98026f3362 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -13,10 +13,10 @@ #include <arch/io.h> #include <cbfs.h> +#include <cf9_reset.h> #include <console/console.h> #include <fsp/util.h> #include <lib.h> -#include <reset.h> #include <string.h> static bool looks_like_fsp_header(const uint8_t *raw_hdr) @@ -109,10 +109,10 @@ void fsp_handle_reset(uint32_t status) switch (status) { case FSP_STATUS_RESET_REQUIRED_COLD: - hard_reset(); + full_reset(); break; case FSP_STATUS_RESET_REQUIRED_WARM: - soft_reset(); + system_reset(); break; case FSP_STATUS_RESET_REQUIRED_3: case FSP_STATUS_RESET_REQUIRED_4: diff --git a/src/include/reset.h b/src/include/reset.h index fe6328d2d9..3eec193c84 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -39,8 +39,6 @@ __noreturn void board_reset(void); */ void do_board_reset(void); -/* Super-hard reset specific to some Intel SoCs. */ -__noreturn void global_reset(void); /* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */ __noreturn void hard_reset(void); /* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */ @@ -48,19 +46,7 @@ __noreturn void soft_reset(void); /* Reset implementations. Implement these in SoC or mainboard code. Implement at least hard_reset() if possible, others fall back to it if necessary. */ -void do_global_reset(void); void do_hard_reset(void); void do_soft_reset(void); -enum reset_type { /* listed in order of softness */ - GLOBAL_RESET, - HARD_RESET, - SOFT_RESET, -}; - -/* Callback that an SoC may override to perform special actions before reset. - Take into account that softer resets may fall back to harder resets if not - implemented... this will *not* trigger another callback! */ -void soc_reset_prepare(enum reset_type reset_type); - #endif diff --git a/src/lib/reset.c b/src/lib/reset.c index 283f72c2bf..4b19e1e7e6 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -51,24 +51,11 @@ __noreturn static void __hard_reset(void) { } /* Not all platforms implement all reset types. Fall back to hard_reset. */ -__weak void do_global_reset(void) { __hard_reset(); } __weak void do_soft_reset(void) { __hard_reset(); } -__weak void soc_reset_prepare(enum reset_type rt) { /* no-op */ } - -void global_reset(void) -{ - printk(BIOS_INFO, "%s() called!\n", __func__); - soc_reset_prepare(GLOBAL_RESET); - dcache_clean_all(); - do_global_reset(); - halt(); -} - void hard_reset(void) { printk(BIOS_INFO, "%s() called!\n", __func__); - soc_reset_prepare(HARD_RESET); dcache_clean_all(); __hard_reset(); } @@ -76,7 +63,6 @@ void hard_reset(void) void soft_reset(void) { printk(BIOS_INFO, "%s() called!\n", __func__); - soc_reset_prepare(SOFT_RESET); dcache_clean_all(); do_soft_reset(); halt(); diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 81709422d0..1872ed0feb 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -104,7 +104,8 @@ config CPU_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK select UDK_2017_BINDING if SOC_INTEL_GLK - select HAVE_HARD_RESET + select SOC_INTEL_COMMON_RESET + select HAVE_CF9_RESET_PREPARE select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_FSP_GOP select NO_UART_ON_SUPERIO @@ -130,10 +131,6 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. -config SOC_INTEL_COMMON_RESET - bool - default y - config PCR_BASE_ADDRESS hex default 0xd0000000 diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 6ea7a5998e..36bf77b240 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -13,12 +13,13 @@ * GNU General Public License for more details. */ +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> #include <fsp/util.h> #include <intelblocks/pmclib.h> -#include <reset.h> #include <soc/heci.h> +#include <soc/intel/common/reset.h> #include <soc/pm.h> #include <timer.h> @@ -27,10 +28,10 @@ void do_global_reset(void) { pmc_global_reset_enable(1); - hard_reset(); + do_full_reset(); } -void soc_reset_prepare(enum reset_type reset_type) +void cf9_reset_prepare(void) { struct stopwatch sw; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 995564d717..d2ec6c1fa8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -24,6 +24,7 @@ #include <bootmode.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/pae.h> @@ -38,7 +39,6 @@ #include <intelblocks/systemagent.h> #include <intelblocks/pmclib.h> #include <mrc_cache.h> -#include <reset.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/meminit.h> @@ -285,7 +285,7 @@ static void check_full_retrain(const FSPM_UPD *mupd) if (ps->gen_pmcon1 & WARM_RESET_STS) { printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n"); - hard_reset(); + full_reset(); } } diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 2799e5b9af..2ba79926ea 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -20,7 +20,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select HAVE_HARD_RESET select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index ce830f354b..abe029a194 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select GENERIC_GPIO_LIB select HAVE_FSP_GOP - select HAVE_HARD_RESET select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index eae94cf6c5..a6f8092908 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -13,11 +13,12 @@ * GNU General Public License for more details. */ +#include <cf9_reset.h> #include <console/console.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <fsp/util.h> -#include <reset.h> +#include <soc/intel/common/reset.h> #include <string.h> #include <timer.h> #include <soc/pci_devs.h> @@ -85,7 +86,7 @@ void do_global_reset(void) /* global reset if CSE fail to reset */ pmc_global_reset_enable(1); - hard_reset(); + do_full_reset(); } void chipset_handle_reset(uint32_t status) @@ -93,7 +94,7 @@ void chipset_handle_reset(uint32_t status) switch (status) { case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - do_global_reset(); + global_reset(); break; default: printk(BIOS_ERR, "unhandled reset type %x\n", status); diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index ea6f10e1f6..42043d740d 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -25,6 +25,7 @@ config DISPLAY_SMM_MEMORY_MAP config SOC_INTEL_COMMON_RESET bool default n + select HAVE_CF9_RESET config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c2f0594283..870e371233 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -18,7 +18,7 @@ #include <arch/smp/mpspec.h> #include <bootstate.h> #include <cbmem.h> -#include <cpu/intel/reset.h> +#include <cf9_reset.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index bdd7d9198e..71a7b0f02b 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -1,9 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright 2017 Google, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,21 +13,24 @@ * GNU General Public License for more details. */ -#include <arch/hlt.h> -#include <arch/io.h> -#include <cpu/intel/reset.h> +#include <arch/cache.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <halt.h> #include <reset.h> -#if IS_ENABLED(CONFIG_HAVE_HARD_RESET) -void do_hard_reset(void) +#include "reset.h" + +void global_reset(void) { - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + dcache_clean_all(); + do_global_reset(); + halt(); } -#endif -void do_soft_reset(void) +void do_board_reset(void) { - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); + full_reset(); } diff --git a/src/include/cpu/intel/reset.h b/src/soc/intel/common/reset.h index 9cf6168a7c..0e605d6c61 100644 --- a/src/include/cpu/intel/reset.h +++ b/src/soc/intel/common/reset.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -14,13 +12,17 @@ * GNU General Public License for more details. */ -#ifndef CPU_INTEL_RESET_H -#define CPU_INTEL_RESET_H +#ifndef _INTEL_COMMON_RESET_H_ +#define _INTEL_COMMON_RESET_H_ + +/* + * Implement SoC specific global reset (i.e. a reset of both host and + * ME partitions). Usually the ME is asked to perform the reset first. + * If that doesn't work out, fall back to a manual global reset. + */ +void do_global_reset(void); -/* Reset control port */ -#define RST_CNT 0xcf9 -#define FULL_RST (1 << 3) -#define RST_CPU (1 << 2) -#define SYS_RST (1 << 1) +/* Prepare for reset, run do_global_reset(), halt. */ +__noreturn void global_reset(void); -#endif /* CPU_INTEL_RESET_H */ +#endif /* _INTEL_COMMON_RESET_H_ */ diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index e22b8ee081..736d567c17 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -33,7 +33,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select HAVE_HARD_RESET select POSTCAR_STAGE select C_ENVIRONMENT_BOOTBLOCK select IOAPIC diff --git a/src/soc/intel/denverton_ns/reset.c b/src/soc/intel/denverton_ns/reset.c index 97955a574a..577f1c4914 100644 --- a/src/soc/intel/denverton_ns/reset.c +++ b/src/soc/intel/denverton_ns/reset.c @@ -15,13 +15,12 @@ #include <console/console.h> #include <fsp/util.h> -#include <reset.h> void chipset_handle_reset(uint32_t status) { switch (status) { case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ - global_reset(); + die("Global Reset not implemented!\n"); break; default: printk(BIOS_ERR, "unhandled reset type %x\n", status); diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index cf4ae7c1ed..617b64a619 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -15,9 +15,9 @@ */ #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <reset.h> #include <soc/fiamux.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -93,7 +93,7 @@ static void early_pmc_init(void) pci_write_config32(dev, PMC_ETR3, pci_read_config32(dev, PMC_ETR3) | PMC_ETR3_CF9GR); - hard_reset(); + full_reset(); } } } diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 30bb6a2740..232dc4fcc0 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK - select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER select NO_MMCONF_SUPPORT select REG_SCRIPT diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c index b5b86f3489..fe133663a8 100644 --- a/src/soc/intel/quark/reset.c +++ b/src/soc/intel/quark/reset.c @@ -13,13 +13,13 @@ * GNU General Public License for more details. */ +#include <cf9_reset.h> #include <console/console.h> #include <fsp/util.h> -#include <reset.h> void chipset_handle_reset(uint32_t status) { /* Do a hard reset if Quark FSP ever requests a reset */ printk(BIOS_ERR, "Unknown reset type %x\n", status); - hard_reset(); + full_reset(); } diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f7a46bef8d..1452b57d1f 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select GENERIC_GPIO_LIB select HAVE_FSP_GOP - select HAVE_HARD_RESET select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index d9e3ea5062..f73563e05e 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -13,10 +13,11 @@ * GNU General Public License for more details. */ +#include <cf9_reset.h> #include <console/console.h> #include <fsp/util.h> #include <intelblocks/pmclib.h> -#include <reset.h> +#include <soc/intel/common/reset.h> #include <soc/me.h> #include <soc/pm.h> #include <timer.h> @@ -32,7 +33,7 @@ static void do_force_global_reset(void) /* Now BIOS can write 0x06 or 0x0E to 0xCF9 port * to global reset platform */ - hard_reset(); + do_full_reset(); } void do_global_reset(void) |