3 files changed, 42 insertions, 23 deletions

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 68f7fca483..85d174363e 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -8,18 +8,19 @@
 static const struct mb_cfg ddr4_mem_config = {
 	.type = MEM_TYPE_DDR4,
 
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 33, 33, 30},
+	},
+
 	.ect = true, /* Early Command Training */
 
 	.UserBd = BOARD_TYPE_MOBILE,
 
 	.ddr_config = {
-
-		/* Baseboard uses only 100ohm Rcomp resistor */
-		.rcomp_resistor = 100,
-
-		/* Baseboard Rcomp target values */
-		.rcomp_targets = {40, 30, 33, 33, 30},
-
 		.dq_pins_interleaved = false,
 	},
 };
@@ -143,17 +144,19 @@ static const struct mb_cfg lp5_mem_config = {
 static const struct mb_cfg ddr5_mem_config = {
 	.type = MEM_TYPE_DDR5,
 
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 30, 30, 30, 27},
+	},
+
 	.ect = true, /* Early Command Training */
 
 	.UserBd = BOARD_TYPE_MOBILE,
 
 	.ddr_config = {
-		/* Baseboard uses only 100ohm Rcomp resistor */
-		.rcomp_resistor = 100,
-
-		/* Baseboard Rcomp target values */
-		.rcomp_targets = {50, 30, 30, 30, 27},
-
 		.dq_pins_interleaved = false,
 	}
 };
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index 9813d9345e..96e049cf99 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -19,13 +19,6 @@ enum mem_type {
 struct mem_ddr_config {
 	/* Dqs Pins Interleaved Setting. Enable/Disable Control */
 	bool dq_pins_interleaved;
-	/*
-	 * Rcomp resistor value. This values represents the resistance in
-	 * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
-	 */
-	uint16_t rcomp_resistor;
-	/* Rcomp target values. */
-	uint16_t rcomp_targets[5];
 };
 
 struct lpx_dq {
@@ -64,9 +57,22 @@ struct mem_lp5x_config {
 	uint8_t ccc_config;
 };
 
+struct rcomp {
+	/*
+	 * Rcomp resistor value. This values represents the resistance in
+	 * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
+	 *
+	 * Note: If mainboard users don't want to override rcomp related settings
+	 * then associated rcomp UPDs will have its default value.
+	 */
+	uint16_t resistor;
+	/* Rcomp target values. */
+	uint16_t targets[5];
+};
+
 struct mb_cfg {
 	enum mem_type type;
-
+	struct rcomp rcomp;
 	union {
 		/*
 		 * DQ CPU<>DRAM map:
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index dcff61113a..48d338600d 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -14,6 +14,17 @@
 #define DDR5_PHYSICAL_CH_WIDTH		32
 #define DDR5_CHANNELS			CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
 
+static void set_rcomp_config(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg)
+{
+	if (mb_cfg->rcomp.resistor != 0)
+		mem_cfg->RcompResistor = mb_cfg->rcomp.resistor;
+
+	for (size_t i = 0; i < ARRAY_SIZE(mem_cfg->RcompTarget); i++) {
+		if (mb_cfg->rcomp.targets[i] != 0)
+			mem_cfg->RcompTarget[i] = mb_cfg->rcomp.targets[i];
+	}
+}
+
 static void meminit_lp4x(FSP_M_CONFIG *mem_cfg)
 {
 	mem_cfg->DqPinsInterleaved = 0;
@@ -28,8 +39,6 @@ static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp
 static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)
 {
 	mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved;
-	mem_cfg->RcompResistor = ddr_config->rcomp_resistor;
-	memcpy(mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
 }
 
 static const struct soc_mem_cfg soc_mem_cfg[] = {
@@ -215,6 +224,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
 
 	mem_cfg->ECT = mb_cfg->ect;
 	mem_cfg->UserBd = mb_cfg->UserBd;
+	set_rcomp_config(mem_cfg, mb_cfg);
 
 	switch (mb_cfg->type) {
 	case MEM_TYPE_DDR4: