diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 37 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 22 |
2 files changed, 32 insertions, 27 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 74a0020ee3..0f50cc19b0 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -67,25 +67,6 @@ #define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) -#define HECI_OP_MODE_SEC_OVERRIDE 5 - -/* Global Reset Command ID */ -#define MKHI_GLOBAL_RESET_REQ 0xb -#define MKHI_GROUP_ID_CBM 0 - -/* RST Origin */ -#define GR_ORIGIN_BIOS_POST 2 - -#define MKHI_HMRFPO_GROUP_ID 5 - -/* HMRFPO Command Ids */ -#define MKHI_HMRFPO_ENABLE 1 -#define MKHI_HMRFPO_GET_STATUS 3 - -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_TEMP_DISABLE 3 - static struct cse_device { uintptr_t sec_bar; } cse; @@ -258,14 +239,14 @@ static int cse_ready(void) } /* - * Checks if CSE is in SEC_OVERRIDE operation mode. This is the mode where + * Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where * CSE will allow reflashing of CSE region. */ static uint8_t check_cse_sec_override_mode(void) { union me_hfsts1 hfs1; hfs1.data = me_read_config32(PCI_ME_HFSTS1); - if (hfs1.fields.operation_mode == HECI_OP_MODE_SEC_OVERRIDE) + if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG) return 1; return 0; } @@ -591,7 +572,7 @@ int send_heci_reset_req_message(uint8_t rst_type) struct reset_message msg = { .hdr = { .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET_REQ, + .command = MKHI_CBM_GLOBAL_RESET_REQ, }, .req_origin = GR_ORIGIN_BIOS_POST, .reset_type = rst_type @@ -632,7 +613,7 @@ int send_hmrfpo_enable_msg(void) /* HMRFPO Enable message */ struct hmrfpo_enable_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_ENABLE, }, .nonce = {0}, @@ -641,7 +622,9 @@ int send_hmrfpo_enable_msg(void) /* HMRFPO Enable response */ struct hmrfpo_enable_resp { struct mkhi_hdr hdr; + /* Base addr for factory data area, not relevant for client SKUs */ uint32_t fct_base; + /* Length of factory data area, not relevant for client SKUs */ uint32_t fct_limit; uint8_t status; uint8_t padding[3]; @@ -658,9 +641,9 @@ int send_hmrfpo_enable_msg(void) * - Working state is normal and * - Operation mode is normal or temporary disable mode. */ - if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && - hfs1.fields.operation_mode != ME_HFS_TEMP_DISABLE)) { + if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL || + (hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL && + hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) { printk(BIOS_ERR, "HECI: ME not in required Mode\n"); goto failed; } @@ -697,7 +680,7 @@ int send_hmrfpo_get_status_msg(void) struct hmrfpo_get_status_msg msg = { .hdr = { - .group_id = MKHI_HMRFPO_GROUP_ID, + .group_id = MKHI_GROUP_ID_HMRFPO, .command = MKHI_HMRFPO_GET_STATUS, }, }; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index b4bfe68924..751c01d565 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,28 @@ #include <stdint.h> +/* MKHI Command groups */ +#define MKHI_GROUP_ID_CBM 0x0 +#define MKHI_GROUP_ID_HMRFPO 0x5 + +/* Global Reset Command ID */ +#define MKHI_CBM_GLOBAL_RESET_REQ 0xb + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 0x2 + +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 0x1 +#define MKHI_HMRFPO_GET_STATUS 0x3 + +/* ME Current Working States */ +#define ME_HFS1_CWS_NORMAL 0x5 + +/* ME Current Operation Modes */ +#define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 +#define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40, |