summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/ironlake/early_init.c4
-rw-r--r--src/northbridge/intel/ironlake/northbridge.c18
-rw-r--r--src/northbridge/intel/ironlake/quickpath.c551
-rw-r--r--src/northbridge/intel/ironlake/raminit.c733
4 files changed, 646 insertions, 660 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index 767db0d3ba..1e4d0dcc10 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -112,7 +112,7 @@ void ironlake_early_initialization(int chipset_type)
/* Magic for S3 resume. Must be done early. */
if (s3_resume) {
- MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
- MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;
+ mchbar_clrsetbits32(0x1e8, 1, 6);
+ mchbar_clrsetbits32(0x1e8, 3, 4);
}
}
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index 9dc38ec3d4..b5ad824623 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -146,23 +146,15 @@ static void mc_read_resources(struct device *dev)
static void northbridge_init(struct device *dev)
{
- u32 reg32;
-
/* Clear error status bits */
- DMIBAR32(DMIUESTS) = 0xffffffff;
- DMIBAR32(DMICESTS) = 0xffffffff;
+ dmibar_write32(DMIUESTS, 0xffffffff);
+ dmibar_write32(DMICESTS, 0xffffffff);
- reg32 = DMIBAR32(DMILLTC);
- reg32 |= (1 << 29);
- DMIBAR32(DMILLTC) = reg32;
+ dmibar_setbits32(DMILLTC, 1 << 29);
- reg32 = DMIBAR32(0x1f8);
- reg32 |= (1 << 16);
- DMIBAR32(0x1f8) = reg32;
+ dmibar_setbits32(0x1f8, 1 << 16);
- reg32 = DMIBAR32(DMILCTL);
- reg32 |= (1 << 1) | (1 << 0);
- DMIBAR32(DMILCTL) = reg32;
+ dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0);
}
/* Disable unused PEG devices based on devicetree before PCI enumeration */
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index 82fc1e71a8..e0e6f666b6 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -172,9 +172,9 @@ static void compute_274265(struct raminfo *info)
2 * info->cas_latency - 7 + 11);
delay_d_ps += info->revision >= 8 ? 2758 : 4428;
- MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000);
- MCHBAR32_AND_OR(0x138, 0xfaffffff, 0x2000000);
- if ((MCHBAR8(0x144) & 0x1f) > 0x13)
+ mchbar_clrsetbits32(0x140, 7 << 24, 2 << 24);
+ mchbar_clrsetbits32(0x138, 7 << 24, 2 << 24);
+ if ((mchbar_read8(0x144) & 0x1f) > 0x13)
delay_d_ps += 650;
delay_c_ps = delay_d_ps + 1800;
if (delay_c_ps <= delay_a_ps)
@@ -233,16 +233,16 @@ static void program_274265(const struct ram_training *const training)
int channel;
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32((channel << 10) + 0x274) =
+ mchbar_write32((channel << 10) + 0x274,
(training->reg274265[channel][0] << 16) |
- training->reg274265[channel][1];
- MCHBAR16((channel << 10) + 0x265) =
- training->reg274265[channel][2] << 8;
+ training->reg274265[channel][1]);
+ mchbar_write16((channel << 10) + 0x265,
+ training->reg274265[channel][2] << 8);
}
if (training->reg2ca9_bit0)
- MCHBAR8_OR(0x2ca9, 1);
+ mchbar_setbits8(0x2ca9, 1 << 0);
else
- MCHBAR8_AND(0x2ca9, ~1);
+ mchbar_clrbits8(0x2ca9, 1 << 0);
printk(RAM_SPEW, "reg2ca9_bit0 = %x\n", training->reg2ca9_bit0);
@@ -288,11 +288,11 @@ set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
<< 16)
| (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24);
if (reverse) {
- MCHBAR32(reg) = y;
- MCHBAR32(reg + 4) = x;
+ mchbar_write32(reg + 0, y);
+ mchbar_write32(reg + 4, x);
} else {
- MCHBAR32(reg + 4) = y;
- MCHBAR32(reg) = x;
+ mchbar_write32(reg + 4, y);
+ mchbar_write32(reg + 0, x);
}
}
@@ -315,10 +315,10 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2,
| (ratios1.divisor_f4_to_fmax << 16) | (ratios2.
divisor_f4_to_fmax
<< 20));
- MCHBAR32(reg) = ratios1.freq4_to_max_remainder |
- (ratios2.freq4_to_max_remainder << 8) |
- (ratios1.divisor_f4_to_fmax << 16) |
- (ratios2.divisor_f4_to_fmax << 20);
+ mchbar_write32(reg, ratios1.freq4_to_max_remainder |
+ ratios2.freq4_to_max_remainder << 8 |
+ ratios1.divisor_f4_to_fmax << 16 |
+ ratios2.divisor_f4_to_fmax << 20);
}
static void
@@ -331,33 +331,38 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
round_it, add_freqs, &ratios);
switch (mode) {
case 0:
- MCHBAR32(reg + 4) = ratios.freq_diff_reduced |
- (ratios.freqs_reversed << 8);
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.freq4_to_max_remainder << 8) |
- (ratios.divisor_f3_to_fmax << 16) |
- (ratios.divisor_f4_to_fmax << 20) |
- (ratios.freq_min_reduced << 24);
+ mchbar_write32(reg + 4,
+ ratios.freq_diff_reduced |
+ ratios.freqs_reversed << 8);
+ mchbar_write32(reg,
+ ratios.freq3_to_2_remainder |
+ ratios.freq4_to_max_remainder << 8 |
+ ratios.divisor_f3_to_fmax << 16 |
+ ratios.divisor_f4_to_fmax << 20 |
+ ratios.freq_min_reduced << 24);
break;
case 1:
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.divisor_f3_to_fmax << 16);
+ mchbar_write32(reg,
+ ratios.freq3_to_2_remainder |
+ ratios.divisor_f3_to_fmax << 16);
break;
case 2:
- MCHBAR32(reg) = ratios.freq3_to_2_remainder |
- (ratios.freq4_to_max_remainder << 8) |
- (ratios.divisor_f3_to_fmax << 16) |
- (ratios.divisor_f4_to_fmax << 20);
+ mchbar_write32(reg,
+ ratios.freq3_to_2_remainder |
+ ratios.freq4_to_max_remainder << 8 |
+ ratios.divisor_f3_to_fmax << 16 |
+ ratios.divisor_f4_to_fmax << 20);
break;
case 4:
- MCHBAR32(reg) = (ratios.divisor_f3_to_fmax << 4) |
- (ratios.divisor_f4_to_fmax << 8) |
- (ratios.freqs_reversed << 12) |
- (ratios.freq_min_reduced << 16) |
- (ratios.freq_diff_reduced << 24);
+ mchbar_write32(reg,
+ ratios.divisor_f3_to_fmax << 4 |
+ ratios.divisor_f4_to_fmax << 8 |
+ ratios.freqs_reversed << 12 |
+ ratios.freq_min_reduced << 16 |
+ ratios.freq_diff_reduced << 24);
break;
}
}
@@ -393,7 +398,7 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
if (s3resume) {
printk(RAM_SPEW, "[6dc] <= %x\n",
info->cached_training->reg_6dc);
- MCHBAR32(0x6dc) = info->cached_training->reg_6dc;
+ mchbar_write32(0x6dc, info->cached_training->reg_6dc);
} else
set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0,
info->delay46_ps[0], 0,
@@ -405,7 +410,7 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
if (s3resume) {
printk(RAM_SPEW, "[6e8] <= %x\n",
info->cached_training->reg_6e8);
- MCHBAR32(0x6e8) = info->cached_training->reg_6e8;
+ mchbar_write32(0x6e8, info->cached_training->reg_6e8);
} else
set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0,
info->delay46_ps[1], 0,
@@ -425,15 +430,15 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484,
480, 0);
set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0);
- MCHBAR32(0x2dbc) = ((frequency_11(info) / 2) - 1) | 0xe00000;
- MCHBAR32(0x2db8) = ((info->fsb_frequency - 1) << 16) | 0x77;
+ mchbar_write32(0x2dbc, ((frequency_11(info) / 2) - 1) | 0xe00000);
+ mchbar_write32(0x2db8, (info->fsb_frequency - 1) << 16 | 0x77);
}
static u16 quickpath_configure_pll_ratio(struct raminfo *info, const u8 x2ca8)
{
- MCHBAR32_OR(0x18b4, 0x210000);
- MCHBAR32_OR(0x1890, 0x2000000);
- MCHBAR32_OR(0x18b4, 0x8000);
+ mchbar_setbits32(0x18b4, 1 << 21 | 1 << 16);
+ mchbar_setbits32(0x1890, 1 << 25);
+ mchbar_setbits32(0x18b4, 1 << 15);
/* Get maximum supported PLL ratio */
u16 qpi_pll_ratio = (pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS) >> 24 & 0x7f);
@@ -455,13 +460,13 @@ static u16 quickpath_configure_pll_ratio(struct raminfo *info, const u8 x2ca8)
/* Finally, program the ratio */
pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, qpi_pll_ratio);
- const u16 csipll0 = MCHBAR16(0x2c10);
- MCHBAR16(0x2c10) = (qpi_pll_ratio > 26) << 11 | 0x400 | qpi_pll_ratio;
+ const u16 csipll0 = mchbar_read16(0x2c10);
+ mchbar_write16(0x2c10, (qpi_pll_ratio > 26) << 11 | 1 << 10 | qpi_pll_ratio);
- if (csipll0 != MCHBAR16(0x2c10) && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ if (csipll0 != mchbar_read16(0x2c10) && x2ca8 == 0)
+ mchbar_setbits8(0x2ca8, 1 << 0);
- MCHBAR16_OR(0x2c12, 0x100);
+ mchbar_setbits16(0x2c12, 1 << 8);
return qpi_pll_ratio;
}
@@ -473,46 +478,46 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
/* Initialize DDR MPLL first */
if (x2ca8 == 0) {
- MCHBAR8_AND_OR(0x164, 0xd9, info->clock_speed_index == 0 ? 0x24 : 0x26);
+ mchbar_clrsetbits8(0x164, 0x26, info->clock_speed_index == 0 ? 0x24 : 0x26);
/* Program DDR MPLL feedback divider ratio */
- MCHBAR16(0x2c20) = (info->clock_speed_index + 3) * 4;
+ mchbar_write16(0x2c20, (info->clock_speed_index + 3) * 4);
}
const u16 qpi_pll_ratio = quickpath_configure_pll_ratio(info, x2ca8);
- MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080);
+ mchbar_clrsetbits32(0x1804, 0x3, 0x8400080);
pci_update_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0xfffffffc, 0x400080);
- const u32 x1c04 = MCHBAR32(0x1c04) & 0xc01080;
- const u32 x1804 = MCHBAR32(0x1804) & 0xc01080;
+ const u32 x1c04 = mchbar_read32(0x1c04) & 0xc01080;
+ const u32 x1804 = mchbar_read32(0x1804) & 0xc01080;
if (x1c04 != x1804 && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ mchbar_setbits8(0x2ca8, 1 << 0);
- MCHBAR32(0x18d8) = 0x120000;
- MCHBAR32(0x18dc) = 0x30a484a;
+ mchbar_write32(0x18d8, 0x120000);
+ mchbar_write32(0x18dc, 0x30a484a);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a);
- MCHBAR32(0x18d8) = 0x40000;
- MCHBAR32(0x18dc) = 0xb000000;
+ mchbar_write32(0x18d8, 0x40000);
+ mchbar_write32(0x18dc, 0xb000000);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x0);
- MCHBAR32(0x18d8) = 0x180000;
- MCHBAR32(0x18dc) = 0xc0000142;
+ mchbar_write32(0x18d8, 0x180000);
+ mchbar_write32(0x18dc, 0xc0000142);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x20000);
pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x142);
- MCHBAR32(0x18d8) = 0x1e0000;
+ mchbar_write32(0x18d8, 0x1e0000);
- const u32 x18dc = MCHBAR32(0x18dc);
- MCHBAR32(0x18dc) = qpi_pll_ratio < 18 ? 2 : 3;
+ const u32 x18dc = mchbar_read32(0x18dc);
+ mchbar_write32(0x18dc, qpi_pll_ratio < 18 ? 2 : 3);
- if (x18dc != MCHBAR32(0x18dc) && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ if (x18dc != mchbar_read32(0x18dc) && x2ca8 == 0)
+ mchbar_setbits8(0x2ca8, 1 << 0);
reg8 = qpi_pll_ratio > 20 ? 10 : 9;
- MCHBAR32(0x188c) = 0x20bc00 | reg8;
+ mchbar_write32(0x188c, 0x20bc00 | reg8);
pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c00 | reg8);
if (qpi_pll_ratio <= 14)
@@ -522,28 +527,28 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
else
reg8 = 0x51;
- MCHBAR32(0x1a10) = reg8 << 24 | qpi_pll_ratio * 60;
- MCHBAR32_OR(0x18b8, 0x200);
- MCHBAR32_OR(0x1918, 0x300);
+ mchbar_write32(0x1a10, reg8 << 24 | qpi_pll_ratio * 60);
+ mchbar_setbits32(0x18b8, 0x200);
+ mchbar_setbits32(0x1918, 0x300);
if (info->revision > 0x17)
- MCHBAR32_OR(0x18b8, 0xc00);
+ mchbar_setbits32(0x18b8, 0xc00);
reg32 = ((qpi_pll_ratio > 20) + 1) << 16;
- MCHBAR32_AND_OR(0x182c, 0xfff0f0ff, reg32 | 0x200);
+ mchbar_clrsetbits32(0x182c, ~0xfff0f0ff, reg32 | 0x200);
pci_update_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0xfff0f0ff, reg32 | 0x200);
- MCHBAR32_AND(0x1a1c, 0x8fffffff);
- MCHBAR32_OR(0x1a70, 0x100000);
+ mchbar_clrbits32(0x1a1c, 7 << 28);
+ mchbar_setbits32(0x1a70, 1 << 20);
- MCHBAR32_AND(0x18b4, 0xffff7fff);
- MCHBAR32_AND_OR(0x1a68, 0xffebc03f, 0x143800);
+ mchbar_clrbits32(0x18b4, 1 << 15);
+ mchbar_clrsetbits32(0x1a68, 0x00143fc0, 0x143800);
- const u32 x1e68 = MCHBAR32(0x1e68) & 0x143fc0;
- const u32 x1a68 = MCHBAR32(0x1a68) & 0x143fc0;
+ const u32 x1e68 = mchbar_read32(0x1e68) & 0x143fc0;
+ const u32 x1a68 = mchbar_read32(0x1a68) & 0x143fc0;
if (x1e68 != x1a68 && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ mchbar_setbits8(0x2ca8, 1 << 0);
pci_update_config32(QPI_LINK_0, QPI_QPILCL, 0xffffff3f, 0x140000);
@@ -551,21 +556,21 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, (reg32 & 0xfffe4555) | 0x64555);
if (reg32 != pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS) && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ mchbar_setbits8(0x2ca8, 1 << 0);
pci_update_config32(QPI_NON_CORE, MIRROR_PORT_CTL, ~3, 0x80 * 3);
- reg32 = MCHBAR32(0x1af0);
- MCHBAR32(0x1af0) = (reg32 & 0xfdffcf) | 0x1f020000;
+ reg32 = mchbar_read32(0x1af0);
+ mchbar_write32(0x1af0, (reg32 & 0xfdffcf) | 0x1f020000);
- if (reg32 != MCHBAR32(0x1af0) && x2ca8 == 0)
- MCHBAR8_OR(0x2ca8, 1);
+ if (reg32 != mchbar_read32(0x1af0) && x2ca8 == 0)
+ mchbar_setbits8(0x2ca8, 1 << 0);
- MCHBAR32_AND(0x1890, 0xfdffffff);
- MCHBAR32_AND_OR(0x18b4, 0xffff6fff, 0x6000);
- MCHBAR32(0x18a4) = 0x22222222;
- MCHBAR32(0x18a8) = 0x22222222;
- MCHBAR32(0x18ac) = 0x22222;
+ mchbar_clrbits32(0x1890, 1 << 25);
+ mchbar_clrsetbits32(0x18b4, 0xf << 12, 0x6 << 12);
+ mchbar_write32(0x18a4, 0x22222222);
+ mchbar_write32(0x18a8, 0x22222222);
+ mchbar_write32(0x18ac, 0x22222);
}
void late_quickpath_init(struct raminfo *info, const int s3resume)
@@ -582,204 +587,204 @@ void late_quickpath_init(struct raminfo *info, const int s3resume)
set_2dxx_series(info, s3resume);
if (!(deven & 8)) {
- MCHBAR32_AND_OR(0x2cb0, 0, 0x40);
+ mchbar_clrsetbits32(0x2cb0, ~0, 0x40);
}
udelay(1000);
if (deven & 8) {
- MCHBAR32_OR(0xff8, 0x1800);
- MCHBAR32_AND(0x2cb0, 0x00);
+ mchbar_setbits32(0xff8, 3 << 11);
+ mchbar_clrbits32(0x2cb0, ~0);
pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
- MCHBAR8(0x1150);
- MCHBAR8(0x1151);
- MCHBAR8(0x1022);
- MCHBAR8(0x16d0);
- MCHBAR32(0x1300) = 0x60606060;
- MCHBAR32(0x1304) = 0x60606060;
- MCHBAR32(0x1308) = 0x78797a7b;
- MCHBAR32(0x130c) = 0x7c7d7e7f;
- MCHBAR32(0x1310) = 0x60606060;
- MCHBAR32(0x1314) = 0x60606060;
- MCHBAR32(0x1318) = 0x60606060;
- MCHBAR32(0x131c) = 0x60606060;
- MCHBAR32(0x1320) = 0x50515253;
- MCHBAR32(0x1324) = 0x54555657;
- MCHBAR32(0x1328) = 0x58595a5b;
- MCHBAR32(0x132c) = 0x5c5d5e5f;
- MCHBAR32(0x1330) = 0x40414243;
- MCHBAR32(0x1334) = 0x44454647;
- MCHBAR32(0x1338) = 0x48494a4b;
- MCHBAR32(0x133c) = 0x4c4d4e4f;
- MCHBAR32(0x1340) = 0x30313233;
- MCHBAR32(0x1344) = 0x34353637;
- MCHBAR32(0x1348) = 0x38393a3b;
- MCHBAR32(0x134c) = 0x3c3d3e3f;
- MCHBAR32(0x1350) = 0x20212223;
- MCHBAR32(0x1354) = 0x24252627;
- MCHBAR32(0x1358) = 0x28292a2b;
- MCHBAR32(0x135c) = 0x2c2d2e2f;
- MCHBAR32(0x1360) = 0x10111213;
- MCHBAR32(0x1364) = 0x14151617;
- MCHBAR32(0x1368) = 0x18191a1b;
- MCHBAR32(0x136c) = 0x1c1d1e1f;
- MCHBAR32(0x1370) = 0x10203;
- MCHBAR32(0x1374) = 0x4050607;
- MCHBAR32(0x1378) = 0x8090a0b;
- MCHBAR32(0x137c) = 0xc0d0e0f;
- MCHBAR8(0x11cc) = 0x4e;
- MCHBAR32(0x1110) = 0x73970404;
- MCHBAR32(0x1114) = 0x72960404;
- MCHBAR32(0x1118) = 0x6f950404;
- MCHBAR32(0x111c) = 0x6d940404;
- MCHBAR32(0x1120) = 0x6a930404;
- MCHBAR32(0x1124) = 0x68a41404;
- MCHBAR32(0x1128) = 0x66a21404;
- MCHBAR32(0x112c) = 0x63a01404;
- MCHBAR32(0x1130) = 0x609e1404;
- MCHBAR32(0x1134) = 0x5f9c1404;
- MCHBAR32(0x1138) = 0x5c961404;
- MCHBAR32(0x113c) = 0x58a02404;
- MCHBAR32(0x1140) = 0x54942404;
- MCHBAR32(0x1190) = 0x900080a;
- MCHBAR16(0x11c0) = 0xc40b;
- MCHBAR16(0x11c2) = 0x303;
- MCHBAR16(0x11c4) = 0x301;
- MCHBAR32_AND_OR(0x1190, 0, 0x8900080a);
- MCHBAR32(0x11b8) = 0x70c3000;
- MCHBAR8(0x11ec) = 0xa;
- MCHBAR16(0x1100) = 0x800;
- MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800);
- MCHBAR16(0x11ca) = 0xfa;
- MCHBAR32(0x11e4) = 0x4e20;
- MCHBAR8(0x11bc) = 0xf;
- MCHBAR16(0x11da) = 0x19;
- MCHBAR16(0x11ba) = 0x470c;
- MCHBAR32(0x1680) = 0xe6ffe4ff;
- MCHBAR32(0x1684) = 0xdeffdaff;
- MCHBAR32(0x1688) = 0xd4ffd0ff;
- MCHBAR32(0x168c) = 0xccffc6ff;
- MCHBAR32(0x1690) = 0xc0ffbeff;
- MCHBAR32(0x1694) = 0xb8ffb0ff;
- MCHBAR32(0x1698) = 0xa8ff0000;
- MCHBAR32(0x169c) = 0xc00;
- MCHBAR32(0x1290) = 0x5000000;
+ mchbar_read8(0x1150);
+ mchbar_read8(0x1151);
+ mchbar_read8(0x1022);
+ mchbar_read8(0x16d0);
+ mchbar_write32(0x1300, 0x60606060);
+ mchbar_write32(0x1304, 0x60606060);
+ mchbar_write32(0x1308, 0x78797a7b);
+ mchbar_write32(0x130c, 0x7c7d7e7f);
+ mchbar_write32(0x1310, 0x60606060);
+ mchbar_write32(0x1314, 0x60606060);
+ mchbar_write32(0x1318, 0x60606060);
+ mchbar_write32(0x131c, 0x60606060);
+ mchbar_write32(0x1320, 0x50515253);
+ mchbar_write32(0x1324, 0x54555657);
+ mchbar_write32(0x1328, 0x58595a5b);
+ mchbar_write32(0x132c, 0x5c5d5e5f);
+ mchbar_write32(0x1330, 0x40414243);
+ mchbar_write32(0x1334, 0x44454647);
+ mchbar_write32(0x1338, 0x48494a4b);
+ mchbar_write32(0x133c, 0x4c4d4e4f);
+ mchbar_write32(0x1340, 0x30313233);
+ mchbar_write32(0x1344, 0x34353637);
+ mchbar_write32(0x1348, 0x38393a3b);
+ mchbar_write32(0x134c, 0x3c3d3e3f);
+ mchbar_write32(0x1350, 0x20212223);
+ mchbar_write32(0x1354, 0x24252627);
+ mchbar_write32(0x1358, 0x28292a2b);
+ mchbar_write32(0x135c, 0x2c2d2e2f);
+ mchbar_write32(0x1360, 0x10111213);
+ mchbar_write32(0x1364, 0x14151617);
+ mchbar_write32(0x1368, 0x18191a1b);
+ mchbar_write32(0x136c, 0x1c1d1e1f);
+ mchbar_write32(0x1370, 0x10203);
+ mchbar_write32(0x1374, 0x4050607);
+ mchbar_write32(0x1378, 0x8090a0b);
+ mchbar_write32(0x137c, 0xc0d0e0f);
+ mchbar_write8(0x11cc, 0x4e);
+ mchbar_write32(0x1110, 0x73970404);
+ mchbar_write32(0x1114, 0x72960404);
+ mchbar_write32(0x1118, 0x6f950404);
+ mchbar_write32(0x111c, 0x6d940404);
+ mchbar_write32(0x1120, 0x6a930404);
+ mchbar_write32(0x1124, 0x68a41404);
+ mchbar_write32(0x1128, 0x66a21404);
+ mchbar_write32(0x112c, 0x63a01404);
+ mchbar_write32(0x1130, 0x609e1404);
+ mchbar_write32(0x1134, 0x5f9c1404);
+ mchbar_write32(0x1138, 0x5c961404);
+ mchbar_write32(0x113c, 0x58a02404);
+ mchbar_write32(0x1140, 0x54942404);
+ mchbar_write32(0x1190, 0x900080a);
+ mchbar_write16(0x11c0, 0xc40b);
+ mchbar_write16(0x11c2, 0x303);
+ mchbar_write16(0x11c4, 0x301);
+ mchbar_clrsetbits32(0x1190, ~0, 0x8900080a);
+ mchbar_write32(0x11b8, 0x70c3000);
+ mchbar_write8(0x11ec, 0xa);
+ mchbar_write16(0x1100, 0x800);
+ mchbar_clrsetbits32(0x11bc, ~0, 0x1e84800);
+ mchbar_write16(0x11ca, 0xfa);
+ mchbar_write32(0x11e4, 0x4e20);
+ mchbar_write8(0x11bc, 0xf);
+ mchbar_write16(0x11da, 0x19);
+ mchbar_write16(0x11ba, 0x470c);
+ mchbar_write32(0x1680, 0xe6ffe4ff);
+ mchbar_write32(0x1684, 0xdeffdaff);
+ mchbar_write32(0x1688, 0xd4ffd0ff);
+ mchbar_write32(0x168c, 0xccffc6ff);
+ mchbar_write32(0x1690, 0xc0ffbeff);
+ mchbar_write32(0x1694, 0xb8ffb0ff);
+ mchbar_write32(0x1698, 0xa8ff0000);
+ mchbar_write32(0x169c, 0xc00);
+ mchbar_write32(0x1290, 0x5000000);
}
- MCHBAR32(0x124c) = 0x15040d00;
- MCHBAR32(0x1250) = 0x7f0000;
- MCHBAR32(0x1254) = 0x1e220004;
- MCHBAR32(0x1258) = 0x4000004;
- MCHBAR32(0x1278) = 0x0;
- MCHBAR32(0x125c) = 0x0;
- MCHBAR32(0x1260) = 0x0;
- MCHBAR32(0x1264) = 0x0;
- MCHBAR32(0x1268) = 0x0;
- MCHBAR32(0x126c) = 0x0;
- MCHBAR32(0x1270) = 0x0;
- MCHBAR32(0x1274) = 0x0;
+ mchbar_write32(0x124c, 0x15040d00);
+ mchbar_write32(0x1250, 0x7f0000);
+ mchbar_write32(0x1254, 0x1e220004);
+ mchbar_write32(0x1258, 0x4000004);
+ mchbar_write32(0x1278, 0x0);
+ mchbar_write32(0x125c, 0x0);
+ mchbar_write32(0x1260, 0x0);
+ mchbar_write32(0x1264, 0x0);
+ mchbar_write32(0x1268, 0x0);
+ mchbar_write32(0x126c, 0x0);
+ mchbar_write32(0x1270, 0x0);
+ mchbar_write32(0x1274, 0x0);
if (deven & 8) {
- MCHBAR16(0x1214) = 0x320;
- MCHBAR32(0x1600) = 0x40000000;
- MCHBAR32_AND_OR(0x11f4, 0, 0x10000000);
- MCHBAR16_AND_OR(0x1230, 0, 0x8000);
- MCHBAR32(0x1400) = 0x13040020;
- MCHBAR32(0x1404) = 0xe090120;
- MCHBAR32(0x1408) = 0x5120220;
- MCHBAR32(0x140c) = 0x5120330;
- MCHBAR32(0x1410) = 0xe090220;
- MCHBAR32(0x1414) = 0x1010001;
- MCHBAR32(0x1418) = 0x1110000;
- MCHBAR32(0x141c) = 0x9020020;
- MCHBAR32(0x1420) = 0xd090220;
- MCHBAR32(0x1424) = 0x2090220;
- MCHBAR32(0x1428) = 0x2090330;
- MCHBAR32(0x142c) = 0xd090220;
- MCHBAR32(0x1430) = 0x1010001;
- MCHBAR32(0x1434) = 0x1110000;
- MCHBAR32(0x1438) = 0x11040020;
- MCHBAR32(0x143c) = 0x4030220;
- MCHBAR32(0x1440) = 0x1060220;
- MCHBAR32(0x1444) = 0x1060330;
- MCHBAR32(0x1448) = 0x4030220;
- MCHBAR32(0x144c) = 0x1010001;
- MCHBAR32(0x1450) = 0x1110000;
- MCHBAR32(0x1454) = 0x4010020;
- MCHBAR32(0x1458) = 0xb090220;
- MCHBAR32(0x145c) = 0x1090220;
- MCHBAR32(0x1460) = 0x1090330;
- MCHBAR32(0x1464) = 0xb090220;
- MCHBAR32(0x1468) = 0x1010001;
- MCHBAR32(0x146c) = 0x1110000;
- MCHBAR32(0x1470) = 0xf040020;
- MCHBAR32(0x1474) = 0xa090220;
- MCHBAR32(0x1478) = 0x1120220;
- MCHBAR32(0x147c) = 0x1120330;
- MCHBAR32(0x1480) = 0xa090220;
- MCHBAR32(0x1484) = 0x1010001;
- MCHBAR32(0x1488) = 0x1110000;
- MCHBAR32(0x148c) = 0x7020020;
- MCHBAR32(0x1490) = 0x1010220;
- MCHBAR32(0x1494) = 0x10210;
- MCHBAR32(0x1498) = 0x10320;
- MCHBAR32(0x149c) = 0x1010220;
- MCHBAR32(0x14a0) = 0x1010001;
- MCHBAR32(0x14a4) = 0x1110000;
- MCHBAR32(0x14a8) = 0xd040020;
- MCHBAR32(0x14ac) = 0x8090220;
- MCHBAR32(0x14b0) = 0x1111310;
- MCHBAR32(0x14b4) = 0x1111420;
- MCHBAR32(0x14b8) = 0x8090220;
- MCHBAR32(0x14bc) = 0x1010001;
- MCHBAR32(0x14c0) = 0x1110000;
- MCHBAR32(0x14c4) = 0x3010020;
- MCHBAR32(0x14c8) = 0x7090220;
- MCHBAR32(0x14cc) = 0x1081310;
- MCHBAR32(0x14d0) = 0x1081420;
- MCHBAR32(0x14d4) = 0x7090220;
- MCHBAR32(0x14d8) = 0x1010001;
- MCHBAR32(0x14dc) = 0x1110000;
- MCHBAR32(0x14e0) = 0xb040020;
- MCHBAR32(0x14e4) = 0x2030220;
- MCHBAR32(0x14e8) = 0x1051310;
- MCHBAR32(0x14ec) = 0x1051420;
- MCHBAR32(0x14f0) = 0x2030220;
- MCHBAR32(0x14f4) = 0x1010001;
- MCHBAR32(0x14f8) = 0x1110000;
- MCHBAR32(0x14fc) = 0x5020020;
- MCHBAR32(0x1500) = 0x5090220;
- MCHBAR32(0x1504) = 0x2071310;
- MCHBAR32(0x1508) = 0x2071420;
- MCHBAR32(0x150c) = 0x5090220;
- MCHBAR32(0x1510) = 0x1010001;
- MCHBAR32(0x1514) = 0x1110000;
- MCHBAR32(0x1518) = 0x7040120;
- MCHBAR32(0x151c) = 0x2090220;
- MCHBAR32(0x1520) = 0x70b1210;
- MCHBAR32(0x1524) = 0x70b1310;
- MCHBAR32(0x1528) = 0x2090220;
- MCHBAR32(0x152c) = 0x1010001;
- MCHBAR32(0x1530) = 0x1110000;
- MCHBAR32(0x1534) = 0x1010110;
- MCHBAR32(0x1538) = 0x1081310;
- MCHBAR32(0x153c) = 0x5041200;
- MCHBAR32(0x1540) = 0x5041310;
- MCHBAR32(0x1544) = 0x1081310;
- MCHBAR32(0x1548) = 0x1010001;
- MCHBAR32(0x154c) = 0x1110000;
- MCHBAR32(0x1550) = 0x1040120;
- MCHBAR32(0x1554) = 0x4051210;
- MCHBAR32(0x1558) = 0xd051200;
- MCHBAR32(0x155c) = 0xd051200;
- MCHBAR32(0x1560) = 0x4051210;
- MCHBAR32(0x1564) = 0x1010001;
- MCHBAR32(0x1568) = 0x1110000;
- MCHBAR16(0x1222) = 0x220a;
- MCHBAR16(0x123c) = 0x1fc0;
- MCHBAR16(0x1220) = 0x1388;
+ mchbar_write16(0x1214, 0x320);
+ mchbar_write32(0x1600, 0x40000000);
+ mchbar_clrsetbits32(0x11f4, ~0, 1 << 28);
+ mchbar_clrsetbits16(0x1230, ~0, 1 << 15);
+ mchbar_write32(0x1400, 0x13040020);
+ mchbar_write32(0x1404, 0xe090120);
+ mchbar_write32(0x1408, 0x5120220);
+ mchbar_write32(0x140c, 0x5120330);
+ mchbar_write32(0x1410, 0xe090220);
+ mchbar_write32(0x1414, 0x1010001);
+ mchbar_write32(0x1418, 0x1110000);
+ mchbar_write32(0x141c, 0x9020020);
+ mchbar_write32(0x1420, 0xd090220);
+ mchbar_write32(0x1424, 0x2090220);
+ mchbar_write32(0x1428, 0x2090330);
+ mchbar_write32(0x142c, 0xd090220);
+ mchbar_write32(0x1430, 0x1010001);
+ mchbar_write32(0x1434, 0x1110000);
+ mchbar_write32(0x1438, 0x11040020);
+ mchbar_write32(0x143c, 0x4030220);
+ mchbar_write32(0x1440, 0x1060220);
+ mchbar_write32(0x1444, 0x1060330);
+ mchbar_write32(0x1448, 0x4030220);
+ mchbar_write32(0x144c, 0x1010001);
+ mchbar_write32(0x1450, 0x1110000);
+ mchbar_write32(0x1454, 0x4010020);
+ mchbar_write32(0x1458, 0xb090220);
+ mchbar_write32(0x145c, 0x1090220);
+ mchbar_write32(0x1460, 0x1090330);
+ mchbar_write32(0x1464, 0xb090220);
+ mchbar_write32(0x1468, 0x1010001);
+ mchbar_write32(0x146c, 0x1110000);
+ mchbar_write32(0x1470, 0xf040020);
+ mchbar_write32(0x1474, 0xa090220);
+ mchbar_write32(0x1478, 0x1120220);
+ mchbar_write32(0x147c, 0x1120330);
+ mchbar_write32(0x1480, 0xa090220);
+ mchbar_write32(0x1484, 0x1010001);
+ mchbar_write32(0x1488, 0x1110000);
+ mchbar_write32(0x148c, 0x7020020);
+ mchbar_write32(0x1490, 0x1010220);
+ mchbar_write32(0x1494, 0x10210);
+ mchbar_write32(0x1498, 0x10320);
+ mchbar_write32(0x149c, 0x1010220);
+ mchbar_write32(0x14a0, 0x1010001);
+ mchbar_write32(0x14a4, 0x1110000);
+ mchbar_write32(0x14a8, 0xd040020);
+ mchbar_write32(0x14ac, 0x8090220);
+ mchbar_write32(0x14b0, 0x1111310);
+ mchbar_write32(0x14b4, 0x1111420);
+ mchbar_write32(0x14b8, 0x8090220);
+ mchbar_write32(0x14bc, 0x1010001);
+ mchbar_write32(0x14c0, 0x1110000);
+ mchbar_write32(0x14c4, 0x3010020);
+ mchbar_write32(0x14c8, 0x7090220);
+ mchbar_write32(0x14cc, 0x1081310);
+ mchbar_write32(0x14d0, 0x1081420);
+ mchbar_write32(0x14d4, 0x7090220);
+ mchbar_write32(0x14d8, 0x1010001);
+ mchbar_write32(0x14dc, 0x1110000);
+ mchbar_write32(0x14e0, 0xb040020);
+ mchbar_write32(0x14e4, 0x2030220);
+ mchbar_write32(0x14e8, 0x1051310);
+ mchbar_write32(0x14ec, 0x1051420);
+ mchbar_write32(0x14f0, 0x2030220);
+ mchbar_write32(0x14f4, 0x1010001);
+ mchbar_write32(0x14f8, 0x1110000);
+ mchbar_write32(0x14fc, 0x5020020);
+ mchbar_write32(0x1500, 0x5090220);
+ mchbar_write32(0x1504, 0x2071310);
+ mchbar_write32(0x1508, 0x2071420);
+ mchbar_write32(0x150c, 0x5090220);
+ mchbar_write32(0x1510, 0x1010001);
+ mchbar_write32(0x1514, 0x1110000);
+ mchbar_write32(0x1518, 0x7040120);
+ mchbar_write32(0x151c, 0x2090220);
+ mchbar_write32(0x1520, 0x70b1210);
+ mchbar_write32(0x1524, 0x70b1310);
+ mchbar_write32(0x1528, 0x2090220);
+ mchbar_write32(0x152c, 0x1010001);
+ mchbar_write32(0x1530, 0x1110000);
+ mchbar_write32(0x1534, 0x1010110);
+ mchbar_write32(0x1538, 0x1081310);
+ mchbar_write32(0x153c, 0x5041200);
+ mchbar_write32(0x1540, 0x5041310);
+ mchbar_write32(0x1544, 0x1081310);
+ mchbar_write32(0x1548, 0x1010001);
+ mchbar_write32(0x154c, 0x1110000);
+ mchbar_write32(0x1550, 0x1040120);
+ mchbar_write32(0x1554, 0x4051210);
+ mchbar_write32(0x1558, 0xd051200);
+ mchbar_write32(0x155c, 0xd051200);
+ mchbar_write32(0x1560, 0x4051210);
+ mchbar_write32(0x1564, 0x1010001);
+ mchbar_write32(0x1568, 0x1110000);
+ mchbar_write16(0x1222, 0x220a);
+ mchbar_write16(0x123c, 0x1fc0);
+ mchbar_write16(0x1220, 0x1388);
}
}
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index af835e2855..4d8fa1328e 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -86,13 +86,12 @@ static void read128(u32 addr, u64 * out)
/* OK */
static void write_1d0(u32 val, u16 addr, int bits, int flag)
{
- MCHBAR32(0x1d0) = 0;
- while (MCHBAR32(0x1d0) & 0x800000)
+ mchbar_write32(0x1d0, 0);
+ while (mchbar_read32(0x1d0) & (1 << 23))
;
- MCHBAR32(0x1d4) =
- (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits);
- MCHBAR32(0x1d0) = 0x40000000 | addr;
- while (MCHBAR32(0x1d0) & 0x800000)
+ mchbar_write32(0x1d4, (val & ((1 << bits) - 1)) | 2 << bits | flag << bits);
+ mchbar_write32(0x1d0, 1 << 30 | addr);
+ while (mchbar_read32(0x1d0) & (1 << 23))
;
}
@@ -100,14 +99,13 @@ static void write_1d0(u32 val, u16 addr, int bits, int flag)
static u16 read_1d0(u16 addr, int split)
{
u32 val;
- MCHBAR32(0x1d0) = 0;
- while (MCHBAR32(0x1d0) & 0x800000)
+ mchbar_write32(0x1d0, 0);
+ while (mchbar_read32(0x1d0) & (1 << 23))
;
- MCHBAR32(0x1d0) =
- 0x80000000 | (((MCHBAR8(0x246) >> 2) & 3) + 0x361 - addr);
- while (MCHBAR32(0x1d0) & 0x800000)
+ mchbar_write32(0x1d0, 1 << 31 | (((mchbar_read8(0x246) >> 2) & 3) + 0x361 - addr));
+ while (mchbar_read32(0x1d0) & (1 << 23))
;
- val = MCHBAR32(0x1d8);
+ val = mchbar_read32(0x1d8);
write_1d0(0, 0x33d, 0, 0);
write_1d0(0, 0x33d, 0, 0);
val &= ((1 << split) - 1);
@@ -148,16 +146,15 @@ static u16
read_500(struct raminfo *info, int channel, u16 addr, int split)
{
u32 val;
- info->last_500_command[channel] = 0x80000000;
- MCHBAR32(0x500 + (channel << 10)) = 0;
- while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
+ info->last_500_command[channel] = 1 << 31;
+ mchbar_write32(0x500 + (channel << 10), 0);
+ while (mchbar_read32(0x500 + (channel << 10)) & (1 << 23))
;
- MCHBAR32(0x500 + (channel << 10)) =
- 0x80000000 | (((MCHBAR8(0x246 + (channel << 10)) >> 2) & 3)
- + 0xb88 - addr);
- while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
+ mchbar_write32(0x500 + (channel << 10),
+ 1 << 31 | (((mchbar_read8(0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
+ while (mchbar_read32(0x500 + (channel << 10)) & (1 << 23))
;
- val = MCHBAR32(0x508 + (channel << 10));
+ val = mchbar_read32(0x508 + (channel << 10));
return val & ((1 << split) - 1);
}
@@ -166,17 +163,17 @@ static void
write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits,
int flag)
{
- if (info->last_500_command[channel] == 0x80000000) {
- info->last_500_command[channel] = 0x40000000;
+ if (info->last_500_command[channel] == 1 << 31) {
+ info->last_500_command[channel] = 1 << 30;
write_500(info, channel, 0, 0xb61, 0, 0);
}
- MCHBAR32(0x500 + (channel << 10)) = 0;
- while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
+ mchbar_write32(0x500 + (channel << 10), 0);
+ while (mchbar_read32(0x500 + (channel << 10)) & (1 << 23))
;
- MCHBAR32(0x504 + (channel << 10)) =
- (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits);
- MCHBAR32(0x500 + (channel << 10)) = 0x40000000 | addr;
- while (MCHBAR32(0x500 + (channel << 10)) & 0x800000)
+ mchbar_write32(0x504 + (channel << 10),
+ (val & ((1 << bits) - 1)) | 2 << bits | flag << bits);
+ mchbar_write32(0x500 + (channel << 10), 1 << 30 | addr);
+ while (mchbar_read32(0x500 + (channel << 10)) & (1 << 23))
;
}
@@ -246,9 +243,9 @@ program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank)
static void write_26c(int channel, u16 si)
{
- MCHBAR32(0x26c + (channel << 10)) = 0x03243f35;
- MCHBAR32(0x268 + (channel << 10)) = 0xcfc00000 | (si << 9);
- MCHBAR16(0x2b9 + (channel << 10)) = si;
+ mchbar_write32(0x26c + (channel << 10), 0x03243f35);
+ mchbar_write32(0x268 + (channel << 10), 0xcfc00000 | si << 9);
+ mchbar_write16(0x2b9 + (channel << 10), si);
}
static void toggle_1d0_142_5ff(void)
@@ -257,8 +254,8 @@ static void toggle_1d0_142_5ff(void)
if (reg32 & (1 << 1))
write_1d0(0, 0x142, 3, 1);
- MCHBAR8(0x5ff) = 0x0;
- MCHBAR8(0x5ff) = 0x80;
+ mchbar_write8(0x5ff, 0);
+ mchbar_write8(0x5ff, 1 << 7);
if (reg32 & (1 << 1))
write_1d0(0x2, 0x142, 3, 1);
}
@@ -267,11 +264,11 @@ static u32 get_580(int channel, u8 addr)
{
u32 ret;
toggle_1d0_142_5ff();
- MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr;
- MCHBAR8_OR(0x580 + (channel << 10), 1);
- while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000))
+ mchbar_write32(0x580 + (channel << 10), 0x8493c012 | addr);
+ mchbar_setbits8(0x580 + (channel << 10), 1 << 0);
+ while (!((ret = mchbar_read32(0x580 + (channel << 10))) & (1 << 16)))
;
- MCHBAR8_AND(0x580 + (channel << 10), ~1);
+ mchbar_clrbits8(0x580 + (channel << 10), 1 << 0);
return ret;
}
@@ -364,8 +361,8 @@ config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
gav(get_580(channel, 0xc | (rank << 5)));
gav(read_1d0(0x142, 3));
- MCHBAR8(0x5ff) = 0x0;
- MCHBAR8(0x5ff) = 0x80;
+ mchbar_write8(0x5ff, 0);
+ mchbar_write8(0x5ff, 1 << 7);
}
static void set_4cf(struct raminfo *info, int channel, u8 bit, u8 val)
@@ -396,28 +393,26 @@ static void set_334(int zero)
c = 0x5f5f;
for (k = 0; k < 2; k++) {
- MCHBAR32(0x138 + 8 * k) =
- (channel << 26) | (j << 24);
+ mchbar_write32(0x138 + 8 * k, channel << 26 | j << 24);
gav(vd8[1][(channel << 3) | (j << 1) | k] =
- MCHBAR32(0x138 + 8 * k));
+ mchbar_read32(0x138 + 8 * k));
gav(vd8[0][(channel << 3) | (j << 1) | k] =
- MCHBAR32(0x13c + 8 * k));
+ mchbar_read32(0x13c + 8 * k));
}
- MCHBAR32(0x334 + (channel << 10) + (j * 0x44)) =
- zero ? 0 : val3[j];
- MCHBAR32(0x32c + (channel << 10) + (j * 0x44)) =
- zero ? 0 : (0x18191819 & lmask);
- MCHBAR16(0x34a + (channel << 10) + (j * 0x44)) = c;
- MCHBAR32(0x33c + (channel << 10) + (j * 0x44)) =
- zero ? 0 : (a & lmask);
- MCHBAR32(0x344 + (channel << 10) + (j * 0x44)) =
- zero ? 0 : (a & lmask);
+ mchbar_write32(0x334 + (channel << 10) + j * 0x44, zero ? 0 : val3[j]);
+ mchbar_write32(0x32c + (channel << 10) + j * 0x44,
+ zero ? 0 : 0x18191819 & lmask);
+ mchbar_write16(0x34a + (channel << 10) + j * 0x44, c);
+ mchbar_write32(0x33c + (channel << 10) + j * 0x44,
+ zero ? 0 : a & lmask);
+ mchbar_write32(0x344 + (channel << 10) + j * 0x44,
+ zero ? 0 : a & lmask);
}
}
- MCHBAR32_OR(0x130, 1);
- while (MCHBAR8(0x130) & 1)
+ mchbar_setbits32(0x130, 1 << 0);
+ while (mchbar_read8(0x130) & 1)
;
}
@@ -798,11 +793,11 @@ static void compute_derived_timings(struct raminfo *info)
else
info->max_slots_used_in_channel = 1;
for (channel = 0; channel < 2; channel++)
- MCHBAR32(0x244 + (channel << 10)) =
+ mchbar_write32(0x244 + (channel << 10),
((info->revision < 8) ? 1 : 0x200) |
((2 - info->max_slots_used_in_channel) << 17) |
(channel << 21) |
- (info->some_delay_1_cycle_floor << 18) | 0x9510;
+ (info->some_delay_1_cycle_floor << 18) | 0x9510);
if (info->max_slots_used_in_channel == 1) {
info->mode4030[0] = (count_ranks_in_channel(info, 0) == 2);
info->mode4030[1] = (count_ranks_in_channel(info, 1) == 2);
@@ -925,8 +920,9 @@ static void jedec_read(struct raminfo *info,
if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) |
((addr3 >> 1) & 0x10);
- MCHBAR8(0x271) = addr3 | (MCHBAR8(0x271) & 0xC1);
- MCHBAR8(0x671) = addr3 | (MCHBAR8(0x671) & 0xC1);
+
+ mchbar_clrsetbits8(0x271, 0x1f << 1, addr3);
+ mchbar_clrsetbits8(0x671, 0x1f << 1, addr3);
/* Handle mirrored mapping. */
if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1))
@@ -936,8 +932,8 @@ static void jedec_read(struct raminfo *info,
read32p((value << 3) | (total_rank << 28));
- MCHBAR8(0x271) = (MCHBAR8(0x271) & 0xC3) | 2;
- MCHBAR8(0x671) = (MCHBAR8(0x671) & 0xC3) | 2;
+ mchbar_clrsetbits8(0x271, 0x1f << 1, 1 << 1);
+ mchbar_clrsetbits8(0x671, 0x1f << 1, 1 << 1);
read32p(total_rank << 28);
}
@@ -1018,11 +1014,11 @@ static void jedec_init(struct raminfo *info)
}
}
- MCHBAR16(0x588 + (channel << 10)) = 0x0;
- MCHBAR16(0x58a + (channel << 10)) = 0x4;
- MCHBAR16(0x58c + (channel << 10)) = rtt | MR1_ODS34OHM;
- MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82;
- MCHBAR16(0x590 + (channel << 10)) = 0x1282;
+ mchbar_write16(0x588 + (channel << 10), 0);
+ mchbar_write16(0x58a + (channel << 10), 4);
+ mchbar_write16(0x58c + (channel << 10), rtt | MR1_ODS34OHM);
+ mchbar_write16(0x58e + (channel << 10), rzq_reg58e | 0x82);
+ mchbar_write16(0x590 + (channel << 10), 0x1282);
for (slot = 0; slot < NUM_SLOTS; slot++)
for (rank = 0; rank < NUM_RANKS; rank++)
@@ -1064,14 +1060,14 @@ static void program_modules_memory_map(struct raminfo *info, int pre_jedec)
pre_jedec ? 256 : (256 << info->
density[channel][slot] >> info->
is_x16_module[channel][slot]);
- MCHBAR8(0x208 + rank + 2 * slot + (channel << 10)) =
+ mchbar_write8(0x208 + rank + 2 * slot + (channel << 10),
(pre_jedec ? (1 | ((1 + 1) << 1)) :
(info->is_x16_module[channel][slot] |
((info->density[channel][slot] + 1) << 1))) |
- 0x80;
+ 0x80);
}
- MCHBAR16(0x200 + (channel << 10) + 4 * slot + 2 * rank) =
- total_mb[channel] >> 6;
+ mchbar_write16(0x200 + (channel << 10) + 4 * slot + 2 * rank,
+ total_mb[channel] >> 6);
}
info->total_memory_mb = total_mb[0] + total_mb[1];
@@ -1081,10 +1077,9 @@ static void program_modules_memory_map(struct raminfo *info, int pre_jedec)
info->non_interleaved_part_mb =
total_mb[0] + total_mb[1] - info->interleaved_part_mb;
channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2;
- MCHBAR32(0x100) = channel_0_non_interleaved |
- (info->non_interleaved_part_mb << 16);
+ mchbar_write32(0x100, channel_0_non_interleaved | info->non_interleaved_part_mb << 16);
if (!pre_jedec)
- MCHBAR16(0x104) = info->interleaved_part_mb;
+ mchbar_write16(0x104, info->interleaved_part_mb);
}
static void program_board_delay(struct raminfo *info)
@@ -1123,13 +1118,11 @@ static void program_board_delay(struct raminfo *info)
|| info->silicon_revision == 3))
rmw_1d0(0x116, 5, 2, 4);
}
- MCHBAR32(0x120) = (1 << (info->max_slots_used_in_channel + 28)) |
- 0x188e7f9f;
+ mchbar_write32(0x120, 1 << (info->max_slots_used_in_channel + 28) | 0x188e7f9f);
- MCHBAR8(0x124) = info->board_lane_delay[4] +
- ((frequency_01(info) + 999) / 1000);
- MCHBAR16(0x125) = 0x1360;
- MCHBAR8(0x127) = 0x40;
+ mchbar_write8(0x124, info->board_lane_delay[4] + (frequency_01(info) + 999) / 1000);
+ mchbar_write16(0x125, 0x1360);
+ mchbar_write8(0x127, 0x40);
if (info->fsb_frequency < frequency_11(info) / 2) {
unsigned int some_delay_2_half_cycles;
high_multiplier = 1;
@@ -1153,33 +1146,32 @@ static void program_board_delay(struct raminfo *info)
(frequency_11(info) * 2 -
4 * (info->fsb_frequency))) >> 3, 7);
}
- if (MCHBAR8(0x2ca9) & 1)
+ if (mchbar_read8(0x2ca9) & 1)
some_delay_3_half_cycles = 3;
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32_OR(0x220 + (channel << 10), 0x18001117);
- MCHBAR32(0x224 + (channel << 10)) =
+ mchbar_setbits32(0x220 + (channel << 10), 0x18001117);
+ mchbar_write32(0x224 + (channel << 10),
(info->max_slots_used_in_channel - 1) |
- ((info->cas_latency - 5 - info->clock_speed_index)
- << 21) | ((info->max_slots_used_in_channel +
- info->cas_latency - cas_latency_shift - 4) << 16) |
- ((info->cas_latency - cas_latency_shift - 4) << 26) |
- ((info->cas_latency - info->clock_speed_index +
+ (info->cas_latency - 5 - info->clock_speed_index)
+ << 21 | (info->max_slots_used_in_channel +
+ info->cas_latency - cas_latency_shift - 4) << 16 |
+ (info->cas_latency - cas_latency_shift - 4) << 26 |
+ (info->cas_latency - info->clock_speed_index +
info->max_slots_used_in_channel - 6) << 8);
- MCHBAR32(0x228 + (channel << 10)) =
- info->max_slots_used_in_channel;
- MCHBAR8(0x239 + (channel << 10)) = 32;
- MCHBAR32(0x248 + (channel << 10)) = (high_multiplier << 24) |
- (some_delay_3_half_cycles << 25) | 0x840000;
- MCHBAR32(0x278 + (channel << 10)) = 0xc362042;
- MCHBAR32(0x27c + (channel << 10)) = 0x8b000062;
- MCHBAR32(0x24c + (channel << 10)) =
- ((!!info->clock_speed_index) << 17) |
- (((2 + info->clock_speed_index -
- (!!info->clock_speed_index))) << 12) | 0x10200;
-
- MCHBAR8(0x267 + (channel << 10)) = 0x4;
- MCHBAR16(0x272 + (channel << 10)) = 0x155;
- MCHBAR32_AND_OR(0x2bc + (channel << 10), 0xFF000000, 0x707070);
+ mchbar_write32(0x228 + (channel << 10), info->max_slots_used_in_channel);
+ mchbar_write8(0x239 + (channel << 10), 32);
+ mchbar_write32(0x248 + (channel << 10), high_multiplier << 24 |
+ some_delay_3_half_cycles << 25 | 0x840000);
+ mchbar_write32(0x278 + (channel << 10), 0xc362042);
+ mchbar_write32(0x27c + (channel << 10), 0x8b000062);
+ mchbar_write32(0x24c + (channel << 10),
+ (!!info->clock_speed_index) << 17 |
+ ((2 + info->clock_speed_index -
+ (!!info->clock_speed_index))) << 12 | 0x10200);
+
+ mchbar_write8(0x267 + (channel << 10), 4);
+ mchbar_write16(0x272 + (channel << 10), 0x155);
+ mchbar_clrsetbits32(0x2bc + (channel << 10), 0xffffff, 0x707070);
write_500(info, channel,
((!info->populated_ranks[channel][1][1])
@@ -1189,7 +1181,7 @@ static void program_board_delay(struct raminfo *info)
0x4c9, 4, 1);
}
- MCHBAR8(0x2c4) = ((1 + (info->clock_speed_index != 0)) << 6) | 0xC;
+ mchbar_write8(0x2c4, (1 + (info->clock_speed_index != 0)) << 6 | 0xc);
{
u8 freq_divisor = 2;
if (info->fsb_frequency == frequency_11(info))
@@ -1198,7 +1190,7 @@ static void program_board_delay(struct raminfo *info)
freq_divisor = 1;
else
freq_divisor = 2;
- MCHBAR32(0x2c0) = (freq_divisor << 11) | 0x6009c400;
+ mchbar_write32(0x2c0, freq_divisor << 11 | 0x6009c400);
}
if (info->board_lane_delay[3] <= 10) {
@@ -1213,48 +1205,46 @@ static void program_board_delay(struct raminfo *info)
if (info->clock_speed_index > 1)
cas_latency_derived++;
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32(0x240 + (channel << 10)) =
+ mchbar_write32(0x240 + (channel << 10),
((info->clock_speed_index == 0) * 0x11000) |
- 0x1002100 | ((2 + info->clock_speed_index) << 4) |
- (info->cas_latency - 3);
+ 0x1002100 | (2 + info->clock_speed_index) << 4 |
+ (info->cas_latency - 3));
write_500(info, channel, (info->clock_speed_index << 1) | 1,
0x609, 6, 1);
write_500(info, channel,
info->clock_speed_index + 2 * info->cas_latency - 7,
0x601, 6, 1);
- MCHBAR32(0x250 + (channel << 10)) =
- ((lane_3_delay + info->clock_speed_index + 9) << 6) |
- (info->board_lane_delay[7] << 2) |
- (info->board_lane_delay[4] << 16) |
- (info->board_lane_delay[1] << 25) |
- (info->board_lane_delay[1] << 29) | 1;
- MCHBAR32(0x254 + (channel << 10)) =
- (info->board_lane_delay[1] >> 3) |
- ((info->board_lane_delay[8] + 4 * info->use_ecc) << 6) |
- 0x80 | (info->board_lane_delay[6] << 1) |
- (info->board_lane_delay[2] << 28) |
- (cas_latency_derived << 16) | 0x4700000;
- MCHBAR32(0x258 + (channel << 10)) =
- ((info->board_lane_delay[5] + info->clock_speed_index +
- 9) << 12) | ((info->clock_speed_index -
- info->cas_latency + 12) << 8) |
- (info->board_lane_delay[2] << 17) |
- (info->board_lane_delay[4] << 24) | 0x47;
- MCHBAR32(0x25c + (channel << 10)) =
- (info->board_lane_delay[1] << 1) |
- (info->board_lane_delay[0] << 8) | 0x1da50000;
- MCHBAR8(0x264 + (channel << 10)) = 0xff;
- MCHBAR8(0x5f8 + (channel << 10)) =
- (cas_latency_shift << 3) | info->use_ecc;
+ mchbar_write32(0x250 + (channel << 10),
+ (lane_3_delay + info->clock_speed_index + 9) << 6 |
+ info->board_lane_delay[7] << 2 |
+ info->board_lane_delay[4] << 16 |
+ info->board_lane_delay[1] << 25 |
+ info->board_lane_delay[1] << 29 | 1);
+ mchbar_write32(0x254 + (channel << 10),
+ info->board_lane_delay[1] >> 3 |
+ (info->board_lane_delay[8] + 4 * info->use_ecc) << 6 |
+ 0x80 | info->board_lane_delay[6] << 1 |
+ info->board_lane_delay[2] << 28 |
+ cas_latency_derived << 16 | 0x4700000);
+ mchbar_write32(0x258 + (channel << 10),
+ (info->board_lane_delay[5] + info->clock_speed_index + 9) << 12 |
+ (info->clock_speed_index - info->cas_latency + 12) << 8 |
+ info->board_lane_delay[2] << 17 |
+ info->board_lane_delay[4] << 24 | 0x47);
+ mchbar_write32(0x25c + (channel << 10),
+ info->board_lane_delay[1] << 1 |
+ info->board_lane_delay[0] << 8 | 0x1da50000);
+ mchbar_write8(0x264 + (channel << 10), 0xff);
+ mchbar_write8(0x5f8 + (channel << 10), cas_latency_shift << 3 | info->use_ecc);
}
program_modules_memory_map(info, 1);
- MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9)
- | (MCHBAR16(0x610) & 0x1C3) | 0x3C;
- MCHBAR16_OR(0x612, 0x100);
- MCHBAR16_OR(0x214, 0x3E00);
+ mchbar_clrsetbits16(0x610, 0xfe3c,
+ MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9 | 0x3c);
+ mchbar_setbits16(0x612, 1 << 8);
+ mchbar_setbits16(0x214, 0x3e00);
for (i = 0; i < 8; i++) {
pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i),
(info->total_memory_mb - 64) | !i | 2);
@@ -1491,15 +1481,14 @@ static void save_timings(struct raminfo *info)
for (channel = 0; channel < NUM_CHANNELS; channel++) {
u32 reg32;
- reg32 = MCHBAR32((channel << 10) + 0x274);
+ reg32 = mchbar_read32((channel << 10) + 0x274);
train.reg274265[channel][0] = reg32 >> 16;
train.reg274265[channel][1] = reg32 & 0xffff;
- train.reg274265[channel][2] =
- MCHBAR16((channel << 10) + 0x265) >> 8;
+ train.reg274265[channel][2] = mchbar_read16((channel << 10) + 0x265) >> 8;
}
- train.reg2ca9_bit0 = MCHBAR8(0x2ca9) & 1;
- train.reg_6dc = MCHBAR32(0x6dc);
- train.reg_6e8 = MCHBAR32(0x6e8);
+ train.reg2ca9_bit0 = mchbar_read8(0x2ca9) & 1;
+ train.reg_6dc = mchbar_read32(0x6dc);
+ train.reg_6e8 = mchbar_read32(0x6e8);
printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc);
printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8);
@@ -1710,23 +1699,23 @@ static void setup_heci_uma(struct raminfo *info)
pci_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- DMIBAR32(DMIVC0RCTL) &= ~0x80;
+ dmibar_clrbits32(DMIVC0RCTL, 1 << 7);
RCBA32(0x14) &= ~0x80;
- DMIBAR32(DMIVC1RCTL) &= ~0x80;
+ dmibar_clrbits32(DMIVC1RCTL, 1 << 7);
RCBA32(0x20) &= ~0x80;
- DMIBAR32(DMIVCPRCTL) &= ~0x80;
+ dmibar_clrbits32(DMIVCPRCTL, 1 << 7);
RCBA32(0x30) &= ~0x80;
- DMIBAR32(DMIVCMRCTL) &= ~0x80;
+ dmibar_clrbits32(DMIVCMRCTL, 1 << 7);
RCBA32(0x40) &= ~0x80;
RCBA32(0x40) = 0x87000080; // OK
- DMIBAR32(DMIVCMRCTL) = 0x87000080; // OK
+ dmibar_write32(DMIVCMRCTL, 0x87000080); // OK
- while ((RCBA16(0x46) & 2) && DMIBAR16(DMIVCMRSTS) & VCMNP)
+ while ((RCBA16(0x46) & 2) && dmibar_read16(DMIVCMRSTS) & VCMNP)
;
}
- MCHBAR32(0x24) = 0x10000 + info->memory_reserved_for_heci_mb;
+ mchbar_write32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
send_heci_uma_message(heci_uma_addr, info->memory_reserved_for_heci_mb);
@@ -2126,7 +2115,7 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1);
write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1);
failmask = check_testing(info, total_rank, 0);
- MCHBAR32_OR(0xfb0, 0x00030000);
+ mchbar_setbits32(0xfb0, 3 << 16);
do_fsm(state, count, failmask, 5, 47, lower_usable,
upper_usable, reg1b3);
}
@@ -2191,7 +2180,7 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
check_testing_type2(info, total_rank, 3, i,
1);
}
- MCHBAR32_OR(0xfb0, 0x00030000);
+ mchbar_setbits32(0xfb0, 3 << 16);
for (lane = 0; lane < 8; lane++)
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
@@ -2292,7 +2281,7 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank,
1);
}
- MCHBAR32_OR(0xfb0, 0x00030000);
+ mchbar_setbits32(0xfb0, 3 << 16);
for (lane = 0; lane < 8; lane++) {
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
@@ -2414,12 +2403,12 @@ static void set_ecc(int onoff)
int channel;
for (channel = 0; channel < NUM_CHANNELS; channel++) {
u8 t;
- t = MCHBAR8((channel << 10) + 0x5f8);
+ t = mchbar_read8((channel << 10) + 0x5f8);
if (onoff)
t |= 1;
else
t &= ~1;
- MCHBAR8((channel << 10) + 0x5f8) = t;
+ mchbar_write8((channel << 10) + 0x5f8, t);
}
}
@@ -2719,10 +2708,10 @@ static int try_cached_training(struct raminfo *info)
sizeof(info->training.timing_offset));
write_1d0(2, 0x142, 3, 1);
- saved_243[0] = MCHBAR8(0x243);
- saved_243[1] = MCHBAR8(0x643);
- MCHBAR8(0x243) = saved_243[0] | 2;
- MCHBAR8(0x643) = saved_243[1] | 2;
+ saved_243[0] = mchbar_read8(0x243);
+ saved_243[1] = mchbar_read8(0x643);
+ mchbar_write8(0x243, saved_243[0] | 2);
+ mchbar_write8(0x643, saved_243[1] | 2);
set_ecc(0);
pci_write_config16(NORTHBRIDGE, 0xc8, 3);
if (read_1d0(0x10b, 6) & 1)
@@ -2830,8 +2819,8 @@ static int try_cached_training(struct raminfo *info)
write_1d0(0, 0x1bb, 6, 1);
write_1d0(0, 0x1b3, 6, 1);
write_1d0(0, 0x1a3, 6, 1);
- MCHBAR8(0x243) = saved_243[0];
- MCHBAR8(0x643) = saved_243[1];
+ mchbar_write8(0x243, saved_243[0]);
+ mchbar_write8(0x643, saved_243[1]);
return 1;
@@ -2845,8 +2834,8 @@ fail:
write_1d0(0, 0x1bb, 6, 1);
write_1d0(0, 0x1b3, 6, 1);
write_1d0(0, 0x1a3, 6, 1);
- MCHBAR8(0x243) = saved_243[0];
- MCHBAR8(0x643) = saved_243[1];
+ mchbar_write8(0x243, saved_243[0]);
+ mchbar_write8(0x643, saved_243[1]);
return 0;
}
@@ -2863,10 +2852,10 @@ static void do_ram_training(struct raminfo *info)
u8 reg178_center;
write_1d0(2, 0x142, 3, 1);
- saved_243[0] = MCHBAR8(0x243);
- saved_243[1] = MCHBAR8(0x643);
- MCHBAR8(0x243) = saved_243[0] | 2;
- MCHBAR8(0x643) = saved_243[1] | 2;
+ saved_243[0] = mchbar_read8(0x243);
+ saved_243[1] = mchbar_read8(0x643);
+ mchbar_write8(0x243, saved_243[0] | 2);
+ mchbar_write8(0x643, saved_243[1] | 2);
switch (info->clock_speed_index) {
case 0:
niter = 5;
@@ -3033,8 +3022,8 @@ static void do_ram_training(struct raminfo *info)
try_timing_offsets(info, channel, slot, rank, totalrank);
totalrank++;
}
- MCHBAR8(0x243) = saved_243[0];
- MCHBAR8(0x643) = saved_243[1];
+ mchbar_write8(0x243, saved_243[0]);
+ mchbar_write8(0x643, saved_243[1]);
write_1d0(0, 0x142, 3, 1);
info->training.reg178_center = reg178_center;
}
@@ -3043,8 +3032,8 @@ static void ram_training(struct raminfo *info)
{
u16 saved_fc4;
- saved_fc4 = MCHBAR16(0xfc4);
- MCHBAR16(0xfc4) = 0xffff;
+ saved_fc4 = mchbar_read16(0xfc4);
+ mchbar_write16(0xfc4, 0xffff);
if (info->revision >= 8)
read_4090(info);
@@ -3054,7 +3043,7 @@ static void ram_training(struct raminfo *info)
if ((info->silicon_revision == 2 || info->silicon_revision == 3)
&& info->clock_speed_index < 2)
set_10b(info, 1);
- MCHBAR16(0xfc4) = saved_fc4;
+ mchbar_write16(0xfc4, saved_fc4);
}
u16 get_max_timing(struct raminfo *info, int channel)
@@ -3062,7 +3051,7 @@ u16 get_max_timing(struct raminfo *info, int channel)
int slot, rank, lane;
u16 ret = 0;
- if ((MCHBAR8(0x2ca8) >> 2) < 1)
+ if ((mchbar_read8(0x2ca8) >> 2) < 1)
return 384;
if (info->revision < 8)
@@ -3081,12 +3070,12 @@ u16 get_max_timing(struct raminfo *info, int channel)
static void dmi_setup(void)
{
- gav(DMIBAR8(0x254));
- DMIBAR8(0x254) = 0x1;
- DMIBAR16(0x1b8) = 0x18f2;
- MCHBAR16_AND_OR(0x48, 0, 0x2);
+ gav(dmibar_read8(0x254));
+ dmibar_write8(0x254, 1 << 0);
+ dmibar_write16(0x1b8, 0x18f2);
+ mchbar_clrsetbits16(0x48, ~0, 1 << 1);
- DMIBAR32(0xd68) |= 0x08000000;
+ dmibar_setbits32(0xd68, 1 << 27);
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
@@ -3099,19 +3088,19 @@ void chipset_init(const int s3resume)
u16 ggc;
u8 gfxsize;
- x2ca8 = MCHBAR8(0x2ca8);
+ x2ca8 = mchbar_read8(0x2ca8);
if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
- MCHBAR8(0x2ca8) = 0;
+ mchbar_write8(0x2ca8, 0);
system_reset();
}
dmi_setup();
- MCHBAR16(0x1170) = 0xa880;
- MCHBAR8(0x11c1) = 0x1;
- MCHBAR16(0x1170) = 0xb880;
- MCHBAR8_AND_OR(0x1210, 0, 0x84);
+ mchbar_write16(0x1170, 0xa880);
+ mchbar_write8(0x11c1, 1 << 0);
+ mchbar_write16(0x1170, 0xb880);
+ mchbar_clrsetbits8(0x1210, ~0, 0x84);
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
/* 0 for 32MB */
@@ -3126,11 +3115,11 @@ void chipset_init(const int s3resume)
deven = pci_read_config16(NORTHBRIDGE, DEVEN); // = 0x3
if (deven & 8) {
- MCHBAR8(0x2c30) = 0x20;
+ mchbar_write8(0x2c30, 1 << 5);
pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18
- MCHBAR16_OR(0x2c30, 0x200);
- MCHBAR16(0x2c32) = 0x434;
- MCHBAR32_AND_OR(0x2c44, 0, 0x1053687);
+ mchbar_setbits16(0x2c30, 1 << 9);
+ mchbar_write16(0x2c32, 0x434);
+ mchbar_clrsetbits32(0x2c44, ~0, 0x1053687);
pci_read_config8(GMA, MSAC); // = 0x2
pci_write_config8(GMA, MSAC, 0x2);
RCBA8(0x2318);
@@ -3139,7 +3128,7 @@ void chipset_init(const int s3resume)
RCBA8(0x2320) = 0xfc;
}
- MCHBAR32_AND_OR(0x30, 0, 0x40);
+ mchbar_clrsetbits32(0x30, ~0, 0x40);
pci_write_config16(NORTHBRIDGE, GGC, ggc);
gav(RCBA32(0x3428));
@@ -3162,7 +3151,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
u8 x2ca8;
int cbmem_wasnot_inited;
- x2ca8 = MCHBAR8(0x2ca8);
+ x2ca8 = mchbar_read8(0x2ca8);
printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8);
@@ -3300,7 +3289,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
/* after SPD */
timestamp_add_now(102);
- MCHBAR8_AND(0x2ca8, 0xfc);
+ mchbar_clrbits8(0x2ca8, 1 << 1 | 1 << 0);
collect_system_info(&info);
calculate_timings(&info);
@@ -3337,14 +3326,14 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
if (x2ca8 == 0)
late_quickpath_init(&info, s3resume);
- MCHBAR32_OR(0x2c80, (1 << 24));
- MCHBAR32(0x1804) = MCHBAR32(0x1c04) & ~(1 << 27);
+ mchbar_setbits32(0x2c80, 1 << 24);
+ mchbar_write32(0x1804, mchbar_read32(0x1c04) & ~(1 << 27));
- MCHBAR8(0x2ca8); // !!!!
+ mchbar_read8(0x2ca8); // !!!!
if (x2ca8 == 0) {
- MCHBAR8_AND(0x2ca8, ~3);
- MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"?
+ mchbar_clrbits8(0x2ca8, 3);
+ mchbar_write8(0x2ca8, mchbar_read8(0x2ca8) + 4); // "+" or "|"?
/* This issues a CPU reset without resetting the platform */
printk(BIOS_DEBUG, "Issuing a CPU reset\n");
/* Write back the S3 state to PM1_CNT to let the reset CPU
@@ -3352,26 +3341,26 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
if (s3resume)
write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT)
| (SLP_TYP_S3 << 10));
- MCHBAR32_OR(0x1af0, 0x10);
+ mchbar_setbits32(0x1af0, 1 << 4);
halt();
}
- MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); // !!!!
+ mchbar_clrbits8(0x2ca8, 0); // !!!!
- MCHBAR32_AND(0x2c80, ~(1 << 24));
+ mchbar_clrbits32(0x2c80, 1 << 24);
pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220);
{
- u8 x2c20 = (MCHBAR16(0x2c20) >> 8) & 3;
- u16 x2c10 = MCHBAR16(0x2c10);
- u16 value = MCHBAR16(0x2c00);
+ u8 x2c20 = (mchbar_read16(0x2c20) >> 8) & 3;
+ u16 x2c10 = mchbar_read16(0x2c10);
+ u16 value = mchbar_read16(0x2c00);
if (x2c20 == 0 && (x2c10 & 0x300) == 0)
value |= (1 << 7);
else
value &= ~(1 << 0);
- MCHBAR16(0x2c00) = value;
+ mchbar_write16(0x2c00, value);
}
udelay(1000); // !!!!
@@ -3379,32 +3368,32 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_1d0(0, 0x33d, 0, 0);
write_500(&info, 0, 0, 0xb61, 0, 0);
write_500(&info, 1, 0, 0xb61, 0, 0);
- MCHBAR32(0x1a30) = 0x0;
- MCHBAR32(0x1a34) = 0x0;
- MCHBAR16(0x614) = 0xb5b | (info.populated_ranks[1][0][0] * 0x404) |
- (info.populated_ranks[0][0][0] * 0xa0);
- MCHBAR16(0x616) = 0x26a;
- MCHBAR32(0x134) = 0x856000;
- MCHBAR32(0x160) = 0x5ffffff;
- MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!!
- MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!!
+ mchbar_write32(0x1a30, 0);
+ mchbar_write32(0x1a34, 0);
+ mchbar_write16(0x614, 0xb5b | (info.populated_ranks[1][0][0] * 0x404) |
+ (info.populated_ranks[0][0][0] * 0xa0));
+ mchbar_write16(0x616, 0x26a);
+ mchbar_write32(0x134, 0x856000);
+ mchbar_write32(0x160, 0x5ffffff);
+ mchbar_clrsetbits32(0x114, ~0, 0xc2024440); // !!!!
+ mchbar_clrsetbits32(0x118, ~0, 0x4); // !!!!
for (channel = 0; channel < NUM_CHANNELS; channel++)
- MCHBAR32(0x260 + (channel << 10)) = 0x30809ff |
- ((info.populated_ranks_mask[channel] & 3) << 20);
+ mchbar_write32(0x260 + (channel << 10), 0x30809ff |
+ (info.populated_ranks_mask[channel] & 3) << 20);
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR16(0x31c + (channel << 10)) = 0x101;
- MCHBAR16(0x360 + (channel << 10)) = 0x909;
- MCHBAR16(0x3a4 + (channel << 10)) = 0x101;
- MCHBAR16(0x3e8 + (channel << 10)) = 0x101;
- MCHBAR32(0x320 + (channel << 10)) = 0x29002900;
- MCHBAR32(0x324 + (channel << 10)) = 0x0;
- MCHBAR32(0x368 + (channel << 10)) = 0x32003200;
- MCHBAR16(0x352 + (channel << 10)) = 0x505;
- MCHBAR16(0x354 + (channel << 10)) = 0x3c3c;
- MCHBAR16(0x356 + (channel << 10)) = 0x1040;
- MCHBAR16(0x39a + (channel << 10)) = 0x73e4;
- MCHBAR16(0x3de + (channel << 10)) = 0x77ed;
- MCHBAR16(0x422 + (channel << 10)) = 0x1040;
+ mchbar_write16(0x31c + (channel << 10), 0x101);
+ mchbar_write16(0x360 + (channel << 10), 0x909);
+ mchbar_write16(0x3a4 + (channel << 10), 0x101);
+ mchbar_write16(0x3e8 + (channel << 10), 0x101);
+ mchbar_write32(0x320 + (channel << 10), 0x29002900);
+ mchbar_write32(0x324 + (channel << 10), 0);
+ mchbar_write32(0x368 + (channel << 10), 0x32003200);
+ mchbar_write16(0x352 + (channel << 10), 0x505);
+ mchbar_write16(0x354 + (channel << 10), 0x3c3c);
+ mchbar_write16(0x356 + (channel << 10), 0x1040);
+ mchbar_write16(0x39a + (channel << 10), 0x73e4);
+ mchbar_write16(0x3de + (channel << 10), 0x77ed);
+ mchbar_write16(0x422 + (channel << 10), 0x1040);
}
write_1d0(0x4, 0x151, 4, 1);
@@ -3420,15 +3409,15 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
[0][0]) << 0),
0x1d1, 3, 1);
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR16(0x38e + (channel << 10)) = 0x5f5f;
- MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f;
+ mchbar_write16(0x38e + (channel << 10), 0x5f5f);
+ mchbar_write16(0x3d2 + (channel << 10), 0x5f5f);
}
set_334(0);
program_base_timings(&info);
- MCHBAR8_OR(0x5ff, 0x80);
+ mchbar_setbits8(0x5ff, 1 << 7);
write_1d0(0x2, 0x1d5, 2, 1);
write_1d0(0x20, 0x166, 7, 1);
@@ -3479,20 +3468,20 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1);
}
- MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!!
- MCHBAR32(0x1f0) = 0x1d000200;
- MCHBAR8_OR(0x1f0, 0x1);
- while (MCHBAR8(0x1f0) & 1)
+ mchbar_clrsetbits32(0x1f4, ~0, 1 << 17); // !!!!
+ mchbar_write32(0x1f0, 0x1d000200);
+ mchbar_setbits8(0x1f0, 1 << 0);
+ while (mchbar_read8(0x1f0) & 1)
;
program_board_delay(&info);
- MCHBAR8(0x5ff) = 0x0;
- MCHBAR8(0x5ff) = 0x80;
- MCHBAR8(0x5f4) = 0x1;
+ mchbar_write8(0x5ff, 0);
+ mchbar_write8(0x5ff, 1 << 7);
+ mchbar_write8(0x5f4, 1 << 0);
- MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ?
- while (MCHBAR32(0x130) & 1)
+ mchbar_clrbits32(0x130, 1 << 1); // | 2 when ?
+ while (mchbar_read32(0x130) & 1)
;
rmw_1d0(0x14b, 0x47, 0x30, 7);
@@ -3505,13 +3494,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
rmw_1d0(0x116, 0xe, 0, 4);
rmw_1d0(0xae, 0x3e, 0, 6);
rmw_1d0(0x300, 0x3e, 0, 6);
- MCHBAR16_AND(0x356, 0x7fff);
- MCHBAR16_AND(0x756, 0x7fff);
- MCHBAR32_AND(0x140, ~0x07000000);
- MCHBAR32_AND(0x138, ~0x07000000);
- MCHBAR32(0x130) = 0x31111301;
+ mchbar_clrbits16(0x356, 1 << 15);
+ mchbar_clrbits16(0x756, 1 << 15);
+ mchbar_clrbits32(0x140, 7 << 24);
+ mchbar_clrbits32(0x138, 7 << 24);
+ mchbar_write32(0x130, 0x31111301);
/* Wait until REG130b0 is 1. */
- while (MCHBAR32(0x130) & 1)
+ while (mchbar_read32(0x130) & 1)
;
u8 value_a1;
@@ -3529,7 +3518,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
rmw_1d0(0x116, 0xe, 1, 4); // = 0x4040432 // !!!!
{
- if ((MCHBAR32(0x144) & 0x1f) < 0x13)
+ if ((mchbar_read32(0x144) & 0x1f) < 0x13)
value_a1 += 2;
else
value_a1 += 1;
@@ -3547,9 +3536,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
for (channel = 0; channel < NUM_CHANNELS; channel++)
set_4cf(&info, channel, 2, 0);
- MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) |
- (info.populated_ranks[0][0][0] << 29);
- while (MCHBAR8(0x130) & 1)
+ mchbar_write32(0x130, 0x11111301 | info.populated_ranks[1][0][0] << 30 |
+ info.populated_ranks[0][0][0] << 29);
+ while (mchbar_read8(0x130) & 1)
;
{
@@ -3564,7 +3553,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
set_334(1);
- MCHBAR8(0x1e8) = 0x4;
+ mchbar_write8(0x1e8, 1 << 2);
for (channel = 0; channel < NUM_CHANNELS; channel++) {
write_500(&info, channel,
@@ -3572,29 +3561,29 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
1);
write_500(&info, channel, 0x3, 0x69b, 2, 1);
}
- MCHBAR32_AND_OR(0x2d0, 0xff2c01ff, 0x200000);
- MCHBAR16(0x6c0) = 0x14a0;
- MCHBAR32_AND_OR(0x6d0, 0xff0080ff, 0x8000);
- MCHBAR16(0x232) = 0x8;
+ mchbar_clrsetbits32(0x2d0, ~0xff0c01ff, 0x200000);
+ mchbar_write16(0x6c0, 0x14a0);
+ mchbar_clrsetbits32(0x6d0, ~0xff0000ff, 0x8000);
+ mchbar_write16(0x232, 1 << 3);
/* 0x40004 or 0 depending on ? */
- MCHBAR32_AND_OR(0x234, 0xfffbfffb, 0x40004);
- MCHBAR32_AND_OR(0x34, 0xfffffffd, 5);
- MCHBAR32(0x128) = 0x2150d05;
- MCHBAR8(0x12c) = 0x1f;
- MCHBAR8(0x12d) = 0x56;
- MCHBAR8(0x12e) = 0x31;
- MCHBAR8(0x12f) = 0x0;
- MCHBAR8(0x271) = 0x2;
- MCHBAR8(0x671) = 0x2;
- MCHBAR8(0x1e8) = 0x4;
+ mchbar_clrsetbits32(0x234, 0x40004, 0x40004);
+ mchbar_clrsetbits32(0x34, 0x7, 5);
+ mchbar_write32(0x128, 0x2150d05);
+ mchbar_write8(0x12c, 0x1f);
+ mchbar_write8(0x12d, 0x56);
+ mchbar_write8(0x12e, 0x31);
+ mchbar_write8(0x12f, 0);
+ mchbar_write8(0x271, 1 << 1);
+ mchbar_write8(0x671, 1 << 1);
+ mchbar_write8(0x1e8, 1 << 2);
for (channel = 0; channel < NUM_CHANNELS; channel++)
- MCHBAR32(0x294 + (channel << 10)) =
- (info.populated_ranks_mask[channel] & 3) << 16;
- MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000);
- MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000);
+ mchbar_write32(0x294 + (channel << 10),
+ (info.populated_ranks_mask[channel] & 3) << 16);
+ mchbar_clrsetbits32(0x134, ~0xfc01ffff, 0x10000);
+ mchbar_clrsetbits32(0x134, ~0xfc85ffff, 0x850000);
for (channel = 0; channel < NUM_CHANNELS; channel++)
- MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 |
- ((info.populated_ranks_mask[channel] & 3) << 20));
+ mchbar_clrsetbits32(0x260 + (channel << 10), 0xf << 20, 1 << 27 |
+ (info.populated_ranks_mask[channel] & 3) << 20);
if (!s3resume)
jedec_init(&info);
@@ -3609,28 +3598,28 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
totalrank++;
}
- MCHBAR8(0x12c) = 0x9f;
+ mchbar_write8(0x12c, 0x9f);
- MCHBAR8_AND_OR(0x271, 0xcf, 0xe);
- MCHBAR8_AND_OR(0x671, 0xcf, 0xe);
+ mchbar_clrsetbits8(0x271, 0x3e, 0x0e);
+ mchbar_clrsetbits8(0x671, 0x3e, 0x0e);
if (!s3resume) {
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32(0x294 + (channel << 10)) =
- (info.populated_ranks_mask[channel] & 3) << 16;
- MCHBAR16(0x298 + (channel << 10)) =
+ mchbar_write32(0x294 + (channel << 10),
+ (info.populated_ranks_mask[channel] & 3) << 16);
+ mchbar_write16(0x298 + (channel << 10),
info.populated_ranks[channel][0][0] |
- (info.populated_ranks[channel][0][1] << 5);
- MCHBAR32(0x29c + (channel << 10)) = 0x77a;
+ info.populated_ranks[channel][0][1] << 5);
+ mchbar_write32(0x29c + (channel << 10), 0x77a);
}
- MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
+ mchbar_clrsetbits32(0x2c0, ~0, 0x6009cc00); // !!!!
{
u8 a, b;
- a = MCHBAR8(0x243);
- b = MCHBAR8(0x643);
- MCHBAR8(0x243) = a | 2;
- MCHBAR8(0x643) = b | 2;
+ a = mchbar_read8(0x243);
+ b = mchbar_read8(0x643);
+ mchbar_write8(0x243, a | 2);
+ mchbar_write8(0x643, b | 2);
}
write_1d0(7, 0x19b, 3, 1);
@@ -3638,8 +3627,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_1d0(4, 0x1c6, 4, 1);
write_1d0(4, 0x1cc, 4, 1);
rmw_1d0(0x151, 0xf, 0x4, 4);
- MCHBAR32(0x584) = 0xfffff;
- MCHBAR32(0x984) = 0xfffff;
+ mchbar_write32(0x584, 0xfffff);
+ mchbar_write32(0x984, 0xfffff);
for (channel = 0; channel < NUM_CHANNELS; channel++)
for (slot = 0; slot < NUM_SLOTS; slot++)
@@ -3651,31 +3640,31 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
channel, slot,
rank);
- MCHBAR8(0x243) = 0x1;
- MCHBAR8(0x643) = 0x1;
+ mchbar_write8(0x243, 1);
+ mchbar_write8(0x643, 1);
}
/* was == 1 but is common */
pci_write_config16(NORTHBRIDGE, 0xc8, 3);
write_26c(0, 0x820);
write_26c(1, 0x820);
- MCHBAR32_OR(0x130, 2);
+ mchbar_setbits32(0x130, 1 << 1);
/* end */
if (s3resume) {
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32(0x294 + (channel << 10)) =
- (info.populated_ranks_mask[channel] & 3) << 16;
- MCHBAR16(0x298 + (channel << 10)) =
+ mchbar_write32(0x294 + (channel << 10),
+ (info.populated_ranks_mask[channel] & 3) << 16);
+ mchbar_write16(0x298 + (channel << 10),
info.populated_ranks[channel][0][0] |
- (info.populated_ranks[channel][0][1] << 5);
- MCHBAR32(0x29c + (channel << 10)) = 0x77a;
+ info.populated_ranks[channel][0][1] << 5);
+ mchbar_write32(0x29c + (channel << 10), 0x77a);
}
- MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!!
+ mchbar_clrsetbits32(0x2c0, ~0, 0x6009cc00); // !!!!
}
- MCHBAR32_AND(0xfa4, ~0x01000002);
- MCHBAR32(0xfb0) = 0x2000e019;
+ mchbar_clrbits32(0xfa4, 1 << 24 | 1 << 1);
+ mchbar_write32(0xfb0, 0x2000e019);
/* Before training. */
timestamp_add_now(103);
@@ -3692,32 +3681,32 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
program_total_memory_map(&info);
if (info.non_interleaved_part_mb != 0 && info.interleaved_part_mb != 0)
- MCHBAR8(0x111) = 0x20 | (0 << 2) | (1 << 6) | (0 << 7);
+ mchbar_write8(0x111, 0 << 2 | 1 << 5 | 1 << 6 | 0 << 7);
else if (have_match_ranks(&info, 0, 4) && have_match_ranks(&info, 1, 4))
- MCHBAR8(0x111) = 0x20 | (3 << 2) | (0 << 6) | (1 << 7);
+ mchbar_write8(0x111, 3 << 2 | 1 << 5 | 0 << 6 | 1 << 7);
else if (have_match_ranks(&info, 0, 2) && have_match_ranks(&info, 1, 2))
- MCHBAR8(0x111) = 0x20 | (3 << 2) | (0 << 6) | (0 << 7);
+ mchbar_write8(0x111, 3 << 2 | 1 << 5 | 0 << 6 | 0 << 7);
else
- MCHBAR8(0x111) = 0x20 | (3 << 2) | (1 << 6) | (0 << 7);
-
- MCHBAR32_AND(0xfac, ~0x80000000);
- MCHBAR32(0xfb4) = 0x4800;
- MCHBAR32(0xfb8) = (info.revision < 8) ? 0x20 : 0x0;
- MCHBAR32(0xe94) = 0x7ffff;
- MCHBAR32(0xfc0) = 0x80002040;
- MCHBAR32(0xfc4) = 0x701246;
- MCHBAR8_AND(0xfc8, ~0x70);
- MCHBAR32_OR(0xe5c, 0x1000000);
- MCHBAR32_AND_OR(0x1a70, ~0x00100000, 0x00200000);
- MCHBAR32(0x50) = 0x700b0;
- MCHBAR32(0x3c) = 0x10;
- MCHBAR8(0x1aa8) = (MCHBAR8(0x1aa8) & ~0x35) | 0xa;
- MCHBAR8_OR(0xff4, 0x2);
- MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020);
-
- MCHBAR32(0xd00) = IOMMU_BASE2 | 1;
- MCHBAR32(0xd40) = IOMMU_BASE1 | 1;
- MCHBAR32(0xdc0) = IOMMU_BASE4 | 1;
+ mchbar_write8(0x111, 3 << 2 | 1 << 5 | 1 << 6 | 0 << 7);
+
+ mchbar_clrbits32(0xfac, 1 << 31);
+ mchbar_write32(0xfb4, 0x4800);
+ mchbar_write32(0xfb8, (info.revision < 8) ? 0x20 : 0x0);
+ mchbar_write32(0xe94, 0x7ffff);
+ mchbar_write32(0xfc0, 0x80002040);
+ mchbar_write32(0xfc4, 0x701246);
+ mchbar_clrbits8(0xfc8, 0x70);
+ mchbar_setbits32(0xe5c, 1 << 24);
+ mchbar_clrsetbits32(0x1a70, 3 << 20, 2 << 20);
+ mchbar_write32(0x50, 0x700b0);
+ mchbar_write32(0x3c, 0x10);
+ mchbar_clrsetbits8(0x1aa8, 0x3f, 0xa);
+ mchbar_setbits8(0xff4, 1 << 1);
+ mchbar_clrsetbits32(0xff8, 0xe008, 0x1020);
+
+ mchbar_write32(0xd00, IOMMU_BASE2 | 1);
+ mchbar_write32(0xd40, IOMMU_BASE1 | 1);
+ mchbar_write32(0xdc0, IOMMU_BASE4 | 1);
write32p(IOMMU_BASE1 | 0xffc, 0x80000000);
write32p(IOMMU_BASE2 | 0xffc, 0xc0000000);
@@ -3727,28 +3716,28 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
u32 eax;
eax = info.fsb_frequency / 9;
- MCHBAR32_AND_OR(0xfcc, 0xfffc0000,
+ mchbar_clrsetbits32(0xfcc, 0x3ffff,
(eax * 0x280) | (eax * 0x5000) | eax | 0x40000);
- MCHBAR32(0x20) = 0x33001;
+ mchbar_write32(0x20, 0x33001);
}
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32_AND(0x220 + (channel << 10), ~0x7770);
+ mchbar_clrbits32(0x220 + (channel << 10), 0x7770);
if (info.max_slots_used_in_channel == 1)
- MCHBAR16_OR(0x237 + (channel << 10), 0x0201);
+ mchbar_setbits16(0x237 + (channel << 10), 0x0201);
else
- MCHBAR16_AND(0x237 + (channel << 10), ~0x0201);
+ mchbar_clrbits16(0x237 + (channel << 10), 0x0201);
- MCHBAR8_OR(0x241 + (channel << 10), 1);
+ mchbar_setbits8(0x241 + (channel << 10), 1 << 0);
if (info.clock_speed_index <= 1 && (info.silicon_revision == 2
|| info.silicon_revision == 3))
- MCHBAR32_OR(0x248 + (channel << 10), 0x00102000);
+ mchbar_setbits32(0x248 + (channel << 10), 0x00102000);
else
- MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000);
+ mchbar_clrbits32(0x248 + (channel << 10), 0x00102000);
}
- MCHBAR32_OR(0x115, 0x1000000);
+ mchbar_setbits32(0x115, 1 << 24);
{
u8 al;
@@ -3756,63 +3745,63 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
if (!(info.silicon_revision == 0 || info.silicon_revision == 1))
al += 2;
al |= ((1 << (info.max_slots_used_in_channel - 1)) - 1) << 4;
- MCHBAR32(0x210) = (al << 16) | 0x20;
+ mchbar_write32(0x210, al << 16 | 0x20);
}
for (channel = 0; channel < NUM_CHANNELS; channel++) {
- MCHBAR32(0x288 + (channel << 10)) = 0x70605040;
- MCHBAR32(0x28c + (channel << 10)) = 0xfffec080;
- MCHBAR32(0x290 + (channel << 10)) = 0x282091c |
- ((info.max_slots_used_in_channel - 1) << 0x16);
+ mchbar_write32(0x288 + (channel << 10), 0x70605040);
+ mchbar_write32(0x28c + (channel << 10), 0xfffec080);
+ mchbar_write32(0x290 + (channel << 10), 0x282091c |
+ (info.max_slots_used_in_channel - 1) << 0x16);
}
u32 reg1c;
pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = EPBAR32(EPVC1RCAP); // = 0x8001 // OK
+ reg1c = epbar_read32(EPVC1RCAP); // = 0x8001 // OK
pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- EPBAR32(EPVC1RCAP) = reg1c; // OK
- MCHBAR8(0xe08); // = 0x0
+ epbar_write32(EPVC1RCAP, reg1c); // OK
+ mchbar_read8(0xe08); // = 0x0
pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
- MCHBAR8_OR(0x1210, 2);
- MCHBAR32(0x1200) = 0x8800440;
- MCHBAR32(0x1204) = 0x53ff0453;
- MCHBAR32(0x1208) = 0x19002043;
- MCHBAR16(0x1214) = 0x320;
+ mchbar_setbits8(0x1210, 1 << 1);
+ mchbar_write32(0x1200, 0x8800440);
+ mchbar_write32(0x1204, 0x53ff0453);
+ mchbar_write32(0x1208, 0x19002043);
+ mchbar_write16(0x1214, 0x320);
if (info.revision == 0x10 || info.revision == 0x11) {
- MCHBAR16(0x1214) = 0x220;
- MCHBAR8_OR(0x1210, 0x40);
+ mchbar_write16(0x1214, 0x220);
+ mchbar_setbits8(0x1210, 1 << 6);
}
- MCHBAR8_OR(0x1214, 0x4);
- MCHBAR8(0x120c) = 0x1;
- MCHBAR8(0x1218) = 0x3;
- MCHBAR8(0x121a) = 0x3;
- MCHBAR8(0x121c) = 0x3;
- MCHBAR16(0xc14) = 0x0;
- MCHBAR16(0xc20) = 0x0;
- MCHBAR32(0x1c) = 0x0;
+ mchbar_setbits8(0x1214, 1 << 2);
+ mchbar_write8(0x120c, 1);
+ mchbar_write8(0x1218, 3);
+ mchbar_write8(0x121a, 3);
+ mchbar_write8(0x121c, 3);
+ mchbar_write16(0xc14, 0);
+ mchbar_write16(0xc20, 0);
+ mchbar_write32(0x1c, 0);
/* revision dependent here. */
- MCHBAR16_OR(0x1230, 0x1f07);
+ mchbar_setbits16(0x1230, 0x1f07);
if (info.uma_enabled)
- MCHBAR32_OR(0x11f4, 0x10000000);
+ mchbar_setbits32(0x11f4, 1 << 28);
- MCHBAR16_OR(0x1230, 0x8000);
- MCHBAR8_OR(0x1214, 1);
+ mchbar_setbits16(0x1230, 1 << 15);
+ mchbar_setbits8(0x1214, 1 << 0);
u8 bl, ebpb;
u16 reg_1020;
- reg_1020 = MCHBAR32(0x1020); // = 0x6c733c // OK
- MCHBAR8(0x1070) = 0x1;
+ reg_1020 = mchbar_read32(0x1020); // = 0x6c733c // OK
+ mchbar_write8(0x1070, 1);
- MCHBAR32(0x1000) = 0x100;
- MCHBAR8(0x1007) = 0x0;
+ mchbar_write32(0x1000, 0x100);
+ mchbar_write8(0x1007, 0);
if (reg_1020 != 0) {
- MCHBAR16(0x1018) = 0x0;
+ mchbar_write16(0x1018, 0);
bl = reg_1020 >> 8;
ebpb = reg_1020 & 0xff;
} else {
@@ -3822,42 +3811,42 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
rdmsr(0x1a2);
- MCHBAR32(0x1014) = 0xffffffff;
+ mchbar_write32(0x1014, 0xffffffff);
- MCHBAR32(0x1010) = ((((ebpb + 0x7d) << 7) / bl) & 0xff) * (!!reg_1020);
+ mchbar_write32(0x1010, ((((ebpb + 0x7d) << 7) / bl) & 0xff) * !!reg_1020);
- MCHBAR8(0x101c) = 0xb8;
+ mchbar_write8(0x101c, 0xb8);
- MCHBAR8(0x123e) = (MCHBAR8(0x123e) & 0xf) | 0x60;
+ mchbar_clrsetbits8(0x123e, 0xf0, 0x60);
if (reg_1020 != 0) {
- MCHBAR32_AND_OR(0x123c, ~0x00900000, 0x600000);
- MCHBAR8(0x101c) = 0xb8;
+ mchbar_clrsetbits32(0x123c, 0xf << 20, 0x6 << 20);
+ mchbar_write8(0x101c, 0xb8);
}
setup_heci_uma(&info);
if (info.uma_enabled) {
u16 ax;
- MCHBAR32_OR(0x11b0, 0x4000);
- MCHBAR32_OR(0x11b4, 0x4000);
- MCHBAR16_OR(0x1190, 0x4000);
+ mchbar_setbits32(0x11b0, 1 << 14);
+ mchbar_setbits32(0x11b4, 1 << 14);
+ mchbar_setbits16(0x1190, 1 << 14);
- ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK
- MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080;
- MCHBAR16_OR(0x1170, 0x1000);
+ ax = mchbar_read16(0x1190) & 0xf00; // = 0x480a // OK
+ mchbar_write16(0x1170, ax | (mchbar_read16(0x1170) & 0x107f) | 0x4080);
+ mchbar_setbits16(0x1170, 1 << 12);
udelay(1000);
u16 ecx;
- for (ecx = 0xffff; ecx && (MCHBAR16(0x1170) & 0x1000); ecx--)
+ for (ecx = 0xffff; ecx && (mchbar_read16(0x1170) & (1 << 12)); ecx--)
;
- MCHBAR16_AND(0x1190, ~0x4000);
+ mchbar_clrbits16(0x1190, 1 << 14);
}
pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80);
udelay(10000);
- MCHBAR16(0x2ca8) = 0x8;
+ mchbar_write16(0x2ca8, 1 << 3);
udelay(1000);
dump_timings(&info);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 14:32:50 +0000