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-rw-r--r--src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb1
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb1
-rw-r--r--src/soc/intel/elkhartlake/chip.h3
-rw-r--r--src/soc/intel/elkhartlake/romstage/fsp_params.c3
5 files changed, 1 insertions, 8 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index 0fdc88a7a8..baf0ba12ee 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
- register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
# Display related UPDs
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index d7c3e22f3b..9bb8d8f328 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Disabled"
- register "SmbusEnable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index f74b504e0d..72e4f60cd3 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -14,7 +14,6 @@ chip soc/intel/elkhartlake
# FSP configuration
register "SaGv" = "SaGv_Disabled"
- register "SmbusEnable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 3e1d56e17e..8764657b19 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -227,9 +227,6 @@ struct soc_intel_elkhartlake_config {
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
- /* SMBus */
- uint8_t SmbusEnable;
-
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
uint8_t ScsEmmcDdr50Enabled;
diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index b8aaca78db..5c8c995959 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -64,8 +64,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PchMasterClockGating = 1;
m_cfg->PchMasterPowerGating = 1;
- /* Enable SMBus controller based on config */
- m_cfg->SmbusEnable = config->SmbusEnable;
+ m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
/* Set debug probe type */
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT;