4 files changed, 30 insertions, 7 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index d7a455a681..00210a7fe1 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -179,6 +179,15 @@ int lpc_find_wideio_range(uint16_t start, uint16_t size);
 int lpc_set_wideio_range(uint16_t start, uint16_t size);
 
 uintptr_t lpc_get_spibase(void);
-void lpc_set_spibase(uint32_t base, uint32_t enable);
+
+/*
+ * Sets MMIO base address for SPI controller and eSPI controller (if supported by platform).
+ *
+ * eSPI base = SPI base + 0x10000
+ */
+void lpc_set_spibase(uint32_t base);
+
+/* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */
+void lpc_enable_spi_rom(uint32_t enable);
 
 #endif /* __AMDBLOCKS_LPC_H__ */
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 97ef17c612..c9786e7aa2 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -322,19 +322,29 @@ uintptr_t lpc_get_spibase(void)
 	return (uintptr_t)base;
 }
 
-void lpc_set_spibase(u32 base, u32 enable)
+void lpc_set_spibase(uint32_t base)
 {
-	u32 reg32;
+	uint32_t reg32;
+
+	reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
+
+	reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
+	reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
+
+	pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
+}
+
+void lpc_enable_spi_rom(uint32_t enable)
+{
+	uint32_t reg32;
 
 	/* only two types of CS# enables are allowed */
 	enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;
 
 	reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER);
 
-	reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
 	reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
 	reg32 |= enable;
-	reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
 
 	pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
 }
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 73ab03b643..6308953fc6 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -207,7 +207,9 @@ static uintptr_t sb_init_spi_base(void)
 	if (base)
 		return base;
 
-	lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+	lpc_enable_spi_rom(SPI_ROM_ENABLE);
+
 	return SPI_BASE_ADDRESS;
 }
 
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index ccdedf4bbe..e90fe1b457 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -265,7 +265,9 @@ static uintptr_t sb_init_spi_base(void)
 	if (base)
 		return base;
 
-	lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+	lpc_enable_spi_rom(SPI_ROM_ENABLE);
+
 	return SPI_BASE_ADDRESS;
 }