2 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/gpio.c b/src/mainboard/google/brya/variants/kinox/gpio.c
index 6027435cd3..3460d1c679 100644
--- a/src/mainboard/google/brya/variants/kinox/gpio.c
+++ b/src/mainboard/google/brya/variants/kinox/gpio.c
@@ -70,6 +70,8 @@ static const struct pad_config override_gpio_table[] = {
 	/* F16 : GSXCLK ==> NC */
 	PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 
+	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
 	/* H12 : I2C7_SDA ==> NC */
 	PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 	/* H23 : SRCCLKREQ5# ==> NC */
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb
index 7aa253635e..913ff015f8 100644
--- a/src/mainboard/google/brya/variants/kinox/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb
@@ -7,6 +7,9 @@ fw_config
 end
 
 chip soc/intel/alderlake
+	# GPE configuration
+	register "pmc_gpe0_dw1" = "GPP_H"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -195,6 +198,24 @@ chip soc/intel/alderlake
 				device generic 0 alias dptf_policy on end
 			end
 		end
+		device ref pcie_rp5 on
+			# Enable WLAN PCIE 5 using clk 2
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW1_03"
+				device pci 00.0 on end
+			end
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
+				register "srcclk_pin" = "2"
+				device generic 0 on end
+			end
+		end
 		device ref pcie_rp6 on
 			# Enable PCIe-to-eMMC bridge PCIE 6 using clk 1
 			register "pch_pcie_rp[PCH_RP(6)]" = "{