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-rw-r--r--src/southbridge/amd/sb700/Makefile.inc3
-rw-r--r--src/southbridge/amd/sb700/early_setup.c24
-rw-r--r--src/southbridge/amd/sb700/lpc.c19
-rw-r--r--src/southbridge/amd/sb700/ramtop.c51
-rw-r--r--src/southbridge/amd/sb800/Makefile.inc3
-rw-r--r--src/southbridge/amd/sb800/early_setup.c24
-rw-r--r--src/southbridge/amd/sb800/ramtop.c51
7 files changed, 108 insertions, 67 deletions
diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc
index 538a7c1ccd..d93c9a6d5e 100644
--- a/src/southbridge/amd/sb700/Makefile.inc
+++ b/src/southbridge/amd/sb700/Makefile.inc
@@ -19,4 +19,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
romstage-y += smbus.c
+romstage-y += ramtop.c
+ramstage-y += ramtop.c
+
endif
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 0cd65a6f54..6e072a6f82 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -19,14 +19,12 @@
#include <stdint.h>
#include <option.h>
-#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <reset.h>
-#include <cbmem.h>
#include "sb700.h"
#include "smbus.h"
@@ -841,13 +839,6 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-int acpi_get_sleep_type(void)
-{
- u16 tmp;
- tmp = inw(ACPI_PM1_CNT_BLK);
- return ((tmp & (7 << 10)) >> 10);
-}
-
void set_lpc_sticky_ctl(bool enable)
{
uint8_t byte;
@@ -860,19 +851,4 @@ void set_lpc_sticky_ctl(bool enable)
pmio_write(0xbb, byte);
}
-uintptr_t restore_top_of_low_cacheable(void)
-{
- uint32_t xdata = 0;
- int xnvram_pos = 0xfc, xi;
- if (acpi_get_sleep_type() != 3)
- return 0;
- for (xi = 0; xi < 4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return xdata;
-}
-
#endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 8ee0395ccd..2943b96a94 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -82,25 +82,6 @@ static void lpc_init(device_t dev)
setup_i8254(); /* Initialize i8254 timers */
}
-#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
-int acpi_get_sleep_type(void)
-{
- u16 tmp = inw(ACPI_PM1_CNT_BLK);
- return ((tmp & (7 << 10)) >> 10);
-}
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
- u32 dword = (u32) ramtop;
- int nvram_pos = 0xfc, i;
- for (i = 0; i < 4; i++) {
- outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
- nvram_pos++;
- }
-}
-#endif
-
static void sb700_lpc_read_resources(device_t dev)
{
struct resource *res;
diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/ramtop.c
new file mode 100644
index 0000000000..d306fff6fd
--- /dev/null
+++ b/src/southbridge/amd/sb700/ramtop.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "sb700.h"
+
+int acpi_get_sleep_type(void)
+{
+ u16 tmp;
+ tmp = inw(ACPI_PM1_CNT_BLK);
+ return ((tmp & (7 << 10)) >> 10);
+}
+
+void backup_top_of_low_cacheable(uintptr_t ramtop)
+{
+ u32 dword = (u32) ramtop;
+ int nvram_pos = 0xfc, i;
+ for (i = 0; i < 4; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+}
+
+uintptr_t restore_top_of_low_cacheable(void)
+{
+ uint32_t xdata = 0;
+ int xnvram_pos = 0xfc, xi;
+ for (xi = 0; xi < 4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return xdata;
+}
diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc
index fca4a984cb..e5cdb56c8d 100644
--- a/src/southbridge/amd/sb800/Makefile.inc
+++ b/src/southbridge/amd/sb800/Makefile.inc
@@ -14,4 +14,7 @@ ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+romstage-y += ramtop.c
+ramstage-y += ramtop.c
+
endif
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 9ac66fb45d..badc4a7b05 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -17,10 +17,8 @@
#define _SB800_EARLY_SETUP_C_
#include <reset.h>
-#include <arch/acpi.h>
#include <arch/cpu.h>
#include <southbridge/amd/common/amd_defs.h>
-#include <cbmem.h>
#include "sb800.h"
#include "smbus.c"
@@ -658,26 +656,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-int acpi_get_sleep_type(void)
-{
- u16 tmp;
- tmp = inw(ACPI_PM1_CNT_BLK);
- return ((tmp & (7 << 10)) >> 10);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- uint32_t xdata = 0;
- int xnvram_pos = 0xfc, xi;
- if (acpi_get_sleep_type() != 3)
- return 0;
- for (xi = 0; xi < 4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return xdata;
-}
-
#endif
diff --git a/src/southbridge/amd/sb800/ramtop.c b/src/southbridge/amd/sb800/ramtop.c
new file mode 100644
index 0000000000..889c699379
--- /dev/null
+++ b/src/southbridge/amd/sb800/ramtop.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "sb800.h"
+
+int acpi_get_sleep_type(void)
+{
+ u16 tmp;
+ tmp = inw(ACPI_PM1_CNT_BLK);
+ return ((tmp & (7 << 10)) >> 10);
+}
+
+void backup_top_of_low_cacheable(uintptr_t ramtop)
+{
+ u32 dword = ramtop;
+ int nvram_pos = 0xfc, i;
+ for (i = 0; i < 4; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
+ nvram_pos++;
+ }
+}
+
+uintptr_t restore_top_of_low_cacheable(void)
+{
+ uint32_t xdata = 0;
+ int xnvram_pos = 0xfc, xi;
+ for (xi = 0; xi < 4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return xdata;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 15:06:51 +0000