diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/commonlib/bsd/include/commonlib/bsd/cb_err.h | 7 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 9 | ||||
| -rw-r--r-- | src/include/boot/coreboot_tables.h | 2 | ||||
| -rw-r--r-- | src/lib/coreboot_table.c | 18 |
4 files changed, 33 insertions, 3 deletions
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index eec44f2f1c..725882c602 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -13,9 +13,10 @@ * success. Allocate a new group or errors every 100 values. */ enum cb_err { - CB_SUCCESS = 0, /**< Call completed successfully */ - CB_ERR = -1, /**< Generic error code */ - CB_ERR_ARG = -2, /**< Invalid argument */ + CB_SUCCESS = 0, /**< Call completed successfully */ + CB_ERR = -1, /**< Generic error code */ + CB_ERR_ARG = -2, /**< Invalid argument */ + CB_ERR_NOT_IMPLEMENTED = -3, /**< Function not implemented */ /* NVRAM/CMOS errors */ CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7666588cf6..3f7ff2df29 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -86,6 +86,7 @@ enum { LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, LB_TAG_ACPI_RSDP = 0x0043, + LB_TAG_PCIE = 0x0044, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -144,6 +145,14 @@ struct lb_memory { struct lb_memory_range map[0]; }; +struct lb_pcie { + uint32_t tag; + uint32_t size; + lb_uint64_t ctrl_base; /* Base address of PCIe controller */ +}; +_Static_assert(_Alignof(struct lb_pcie) == 4, + "lb_uint64_t alignment doesn't work as expected for struct lb_pcie!"); + struct lb_hwrpb { uint32_t tag; uint32_t size; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e77c60aad3..7525fda48f 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -21,6 +21,8 @@ void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data); +enum cb_err lb_fill_pcie(struct lb_pcie *pcie); + /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index ebaa3a52f5..2a7ccc5f55 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -33,6 +33,11 @@ void lb_string_platform_blob_version(struct lb_header *header); #endif +__weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +{ + return CB_ERR_NOT_IMPLEMENTED; +} + static struct lb_header *lb_table_init(unsigned long addr) { struct lb_header *header; @@ -118,6 +123,16 @@ void lb_add_console(uint16_t consoletype, void *data) console->type = consoletype; } +static void lb_pcie(struct lb_header *header) +{ + struct lb_pcie pcie = { .tag = LB_TAG_PCIE, .size = sizeof(pcie) }; + + if (lb_fill_pcie(&pcie) != CB_SUCCESS) + return; + + memcpy(lb_new_record(header), &pcie, sizeof(pcie)); +} + static void lb_framebuffer(struct lb_header *header) { struct lb_framebuffer *framebuffer; @@ -483,6 +498,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) if (CONFIG(CONSOLE_USB)) lb_add_console(LB_TAG_CONSOLE_EHCI, head); + if (CONFIG(PCI)) + lb_pcie(head); + /* Record our various random string information */ lb_strings(head); if (CONFIG(PLATFORM_USES_FSP2_0)) |