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-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 1eece7aeed..d1c5c82b2e 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -69,6 +69,14 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[4]" = "0xFF"
register "PcieClkSrcClkReq[5]" = "0xFF"
+ # Disable all L1 substates for PCIe root ports
+ register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
+
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"