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-rw-r--r--src/soc/amd/cezanne/Kconfig1
-rw-r--r--src/soc/amd/cezanne/Makefile.inc1
-rw-r--r--src/soc/amd/cezanne/romstage.c28
-rw-r--r--src/soc/amd/common/block/cpu/Kconfig6
-rw-r--r--src/soc/amd/common/block/cpu/noncar/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/cpu/noncar/romstage.c (renamed from src/soc/amd/mendocino/romstage.c)27
-rw-r--r--src/soc/amd/genoa_poc/Makefile.inc2
-rw-r--r--src/soc/amd/genoa_poc/romstage.c16
-rw-r--r--src/soc/amd/glinda/Kconfig1
-rw-r--r--src/soc/amd/glinda/Makefile.inc1
-rw-r--r--src/soc/amd/glinda/romstage.c28
-rw-r--r--src/soc/amd/mendocino/Kconfig1
-rw-r--r--src/soc/amd/mendocino/Makefile.inc1
-rw-r--r--src/soc/amd/phoenix/Kconfig1
-rw-r--r--src/soc/amd/phoenix/Makefile.inc1
-rw-r--r--src/soc/amd/phoenix/romstage.c28
-rw-r--r--src/soc/amd/picasso/Makefile.inc1
-rw-r--r--src/soc/amd/picasso/romstage.c26
18 files changed, 28 insertions, 143 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 42a7bf335e..0ef658c10f 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -77,6 +77,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
select SOC_AMD_COMMON_BLOCK_XHCI
+ select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
select SSE2
select UDK_2017_BINDING
select USE_DDR4
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 044d33ead2..dedf98c4bd 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -17,7 +17,6 @@ bootblock-y += early_fch.c
bootblock-y += espi_util.c
romstage-y += fsp_m_params.c
-romstage-y += romstage.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
deleted file mode 100644
index 6b84728ad1..0000000000
--- a/src/soc/amd/cezanne/romstage.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- /* Snapshot chipset state prior to any FSP call */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- /* Fixup settings FSP-M should not be changing */
- fch_disable_legacy_dma_io();
-
- memmap_stash_early_dram_usage();
-
- run_ramstage();
-}
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 1ffaece9dd..3dc90ac3b2 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -38,6 +38,12 @@ config ACPI_CPU_STRING
string
default "C%03X"
+config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+ bool
+ help
+ Disable the legacy DMA decodes again after the call into the
+ reference code in romstage to fix up things.
+
endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index f8ca357c40..f3ada6250f 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -8,6 +8,7 @@ bootblock-y += pre_c.S
bootblock-y += write_resume_eip.c
bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock_measure.c
romstage-y += memmap.c
+romstage-y += romstage.c
ramstage-y += cpu.c
romstage-y += cpu.c
ramstage-y += memmap.c
diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/common/block/cpu/noncar/romstage.c
index f1ee595c84..1ce692d568 100644
--- a/src/soc/amd/mendocino/romstage.c
+++ b/src/soc/amd/common/block/cpu/noncar/romstage.c
@@ -2,12 +2,11 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/fsp.h>
+#include <amdblocks/post_codes.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
#include <amdblocks/stb.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
+#include <cbmem.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,13 +17,21 @@ void __noreturn romstage_main(void)
if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
write_stb_to_console();
- /* Snapshot chipset state prior to any FSP call */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- /* Fixup settings FSP-M should not be changing */
- fch_disable_legacy_dma_io();
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE)) {
+ /* Snapshot chipset state prior to any reference code call. */
+ fill_chipset_state();
+ }
+
+ if (CONFIG(PLATFORM_USES_FSP2_0)) {
+ amd_fsp_early_init();
+ } else {
+ cbmem_initialize_empty();
+ }
+
+ if (CONFIG(SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP)) {
+ /* Fix up settings the reference code should not be changing */
+ fch_disable_legacy_dma_io();
+ }
memmap_stash_early_dram_usage();
diff --git a/src/soc/amd/genoa_poc/Makefile.inc b/src/soc/amd/genoa_poc/Makefile.inc
index 7d54254436..01bbe7b8f9 100644
--- a/src/soc/amd/genoa_poc/Makefile.inc
+++ b/src/soc/amd/genoa_poc/Makefile.inc
@@ -11,8 +11,6 @@ all-y += uart.c
bootblock-y += early_fch.c
bootblock-y += aoac.c
-romstage-y += romstage.c
-
ramstage-y += acpi.c
ramstage-y += aoac.c
ramstage-y += chip.c
diff --git a/src/soc/amd/genoa_poc/romstage.c b/src/soc/amd/genoa_poc/romstage.c
deleted file mode 100644
index 66a2140c07..0000000000
--- a/src/soc/amd/genoa_poc/romstage.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/post_codes.h>
-#include <amdblocks/memmap.h>
-#include <cbmem.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- cbmem_initialize_empty();
- memmap_stash_early_dram_usage();
- run_ramstage();
-}
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index b9760489d3..d3194a2412 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -78,6 +78,7 @@ config SOC_AMD_GLINDA
select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+ select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
select SSE2
select UDK_2017_BINDING
select USE_DDR5
diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc
index 675712f6b4..bc217d36d1 100644
--- a/src/soc/amd/glinda/Makefile.inc
+++ b/src/soc/amd/glinda/Makefile.inc
@@ -22,7 +22,6 @@ bootblock-y += espi_util.c
verstage-y += espi_util.c
romstage-y += fsp_m_params.c
-romstage-y += romstage.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
deleted file mode 100644
index 6b84728ad1..0000000000
--- a/src/soc/amd/glinda/romstage.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- /* Snapshot chipset state prior to any FSP call */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- /* Fixup settings FSP-M should not be changing */
- fch_disable_legacy_dma_io();
-
- memmap_stash_early_dram_usage();
-
- run_ramstage();
-}
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index 7192106922..194b775bb0 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -84,6 +84,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_FSP_PCI
select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
+ select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
select SSE2
select UDK_2017_BINDING
select USE_DDR5
diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc
index 6cb098f78b..5b9216e638 100644
--- a/src/soc/amd/mendocino/Makefile.inc
+++ b/src/soc/amd/mendocino/Makefile.inc
@@ -19,7 +19,6 @@ bootblock-y += espi_util.c
verstage-y += espi_util.c
romstage-y += fsp_m_params.c
-romstage-y += romstage.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 5bfb5b9a2b..fd40231827 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -72,6 +72,7 @@ config SOC_AMD_PHOENIX_BASE
select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
select SOC_AMD_COMMON_BLOCK_XHCI
+ select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
select SSE2
select USE_DDR5
select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK
diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc
index 0301cdc0ed..82ce54d91e 100644
--- a/src/soc/amd/phoenix/Makefile.inc
+++ b/src/soc/amd/phoenix/Makefile.inc
@@ -22,7 +22,6 @@ bootblock-y += espi_util.c
verstage-y += espi_util.c
romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c
-romstage-y += romstage.c
romstage-y += soc_util.c
ramstage-y += acpi.c
diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c
deleted file mode 100644
index 6b84728ad1..0000000000
--- a/src/soc/amd/phoenix/romstage.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- /* Snapshot chipset state prior to any FSP call */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- /* Fixup settings FSP-M should not be changing */
- fch_disable_legacy_dma_io();
-
- memmap_stash_early_dram_usage();
-
- run_ramstage();
-}
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 7ca25d0a39..ba58c9178b 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -17,7 +17,6 @@ all_x86-y += uart.c
bootblock-y += early_fch.c
romstage-y += fsp_m_params.c
-romstage-y += romstage.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
deleted file mode 100644
index 5159061b9a..0000000000
--- a/src/soc/amd/picasso/romstage.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/fsp.h>
-#include <amdblocks/memmap.h>
-#include <amdblocks/pmlib.h>
-#include <amdblocks/post_codes.h>
-#include <commonlib/helpers.h>
-#include <console/console.h>
-#include <cpu/cpu.h>
-#include <program_loading.h>
-#include <romstage_common.h>
-#include <types.h>
-
-void __noreturn romstage_main(void)
-{
- post_code(POSTCODE_ROMSTAGE_MAIN);
-
- /* Snapshot chipset state prior to any FSP call. */
- fill_chipset_state();
-
- amd_fsp_early_init();
-
- memmap_stash_early_dram_usage();
-
- run_ramstage();
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:01:03 +0000