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-rw-r--r--src/include/rules.h16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/include/rules.h b/src/include/rules.h
index 523031a809..607d7fc0dd 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -63,13 +63,27 @@
#define ENV_SECMON 0
#define ENV_VERSTAGE 1
-#else
+#elif defined(__RAMSTAGE__)
#define ENV_BOOTBLOCK 0
#define ENV_ROMSTAGE 0
#define ENV_RAMSTAGE 1
#define ENV_SMM 0
#define ENV_SECMON 0
#define ENV_VERSTAGE 0
+
+#else
+/*
+ * Default case of nothing set for random blob generation using
+ * create_class_compiler that isn't bound to a stage. Also AGESA
+ * apparently builds things compeletely separate from coreboot's
+ * build infrastructure -- hardcoding its own rules.
+ */
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+#define ENV_SECMON 0
+#define ENV_VERSTAGE 0
#endif
/* For romstage and ramstage always build with simple device model, ie.