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-rw-r--r--src/acpi/acpi_dmar.c2
-rw-r--r--src/arch/x86/Kconfig12
-rw-r--r--src/arch/x86/cpu_common.c8
-rw-r--r--src/device/pci_device.c2
-rw-r--r--src/include/cpu/cpu.h1
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent.c2
6 files changed, 24 insertions, 3 deletions
diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c
index 83a876c287..9a5ebedbb1 100644
--- a/src/acpi/acpi_dmar.c
+++ b/src/acpi/acpi_dmar.c
@@ -26,7 +26,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
header->length = sizeof(acpi_dmar_t);
header->revision = get_acpi_table_revision(DMAR);
- dmar->host_address_width = cpu_phys_address_size() - 1;
+ dmar->host_address_width = soc_phys_address_size() - 1;
dmar->flags = flags;
current = acpi_fill_dmar(current);
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 90ece988c0..e149f0864e 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -391,4 +391,16 @@ config DUMP_SMBIOS_TYPE17
bool "Dump part of SMBIOS type17 dimm information"
depends on GENERATE_SMBIOS_TABLES
+config SOC_PHYSICAL_ADDRESS_WIDTH
+ int
+ default 0
+ help
+ On some System-on-Chip the physical address size available
+ at the SoC level may be different than at the CPU
+ level. This configuration can be use to set the physical
+ address width (in bits) of the SoC.
+
+ If not set, both CPU and SoC physical address width are
+ assume to be the same.
+
endif
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 0242dcebdd..c4d30a2c06 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -60,6 +60,14 @@ unsigned int cpu_phys_address_size(void)
return 32;
}
+unsigned int soc_phys_address_size(void)
+{
+ if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH)
+ return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH;
+
+ return cpu_phys_address_size();
+}
+
/*
* Get processor id using cpuid eax=1
* return value in EAX register
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 21b43529d7..b356c2695b 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -578,7 +578,7 @@ void pci_domain_read_resources(struct device *dev)
/* Initialize 64-bit memory resource constraints above 4G. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
res->base = 4ULL * GiB;
- res->limit = (1ULL << cpu_phys_address_size()) - 1;
+ res->limit = (1ULL << soc_phys_address_size()) - 1;
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
}
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index 9783976191..5f32720f31 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -10,6 +10,7 @@ void cpu_initialize(void);
uintptr_t cpu_get_lapic_addr(void);
struct bus;
unsigned int cpu_phys_address_size(void);
+unsigned int soc_phys_address_size(void);
#if ENV_RAMSTAGE
#define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver")))
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 58d4dbebf4..24c5a7e5cd 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -313,7 +313,7 @@ void ssdt_set_above_4g_pci(const struct device *dev)
uint64_t touud;
sa_read_map_entry(pcidev_path_on_root(SA_DEVFN_ROOT), &sa_memory_map[SA_TOUUD_REG],
&touud);
- const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
+ const uint64_t len = POWER_OF_2(soc_phys_address_size()) - touud;
const char *scope = acpi_device_path(dev);
acpigen_write_scope(scope);