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-rw-r--r--src/mainboard/libretrend/lt1000/devicetree.cb5
-rw-r--r--src/mainboard/protectli/vault_kbl/devicetree.cb2
-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb2
3 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 2cb674f486..dd2fc6084c 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -38,11 +38,6 @@ chip soc/intel/skylake
[1] = 1,
[2] = 1,
}"
- register "SataPortsDevSlp" = "{
- [0] = 0,
- [1] = 0,
- [2] = 0,
- }"
register "SataSpeedLimit" = "2"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index b824fb4b1b..f57f97832c 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -109,8 +109,6 @@ chip soc/intel/skylake
# Enable SATA ports 1,2
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
- register "SataPortsDevSlp[0]" = "0"
- register "SataPortsDevSlp[1]" = "0"
# Enable Root ports. 1-6 for LAN and Root Port 9
register "PcieRpEnable[0]" = "1"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 0083e641a5..03d48faaa1 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -43,8 +43,6 @@ chip soc/intel/skylake
# FSP Configuration
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
- register "SataPortsDevSlp[0]" = "0"
- register "SataPortsDevSlp[2]" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SkipExtGfxScan" = "1"