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-rw-r--r--src/soc/mediatek/common/dsi.c8
-rw-r--r--src/soc/mediatek/common/include/soc/dsi_common.h1
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 2b4fac7d42..d60abdb964 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -392,6 +392,12 @@ static void mtk_dsi_send_init_commands(const u8 *buf)
}
}
+static void mtk_dsi_reset_dphy(void)
+{
+ setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
+ clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
+}
+
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
const u8 *init_commands)
{
@@ -407,6 +413,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
struct mtk_phy_timing phy_timing;
mtk_dsi_phy_timing(data_rate, &phy_timing);
mtk_dsi_rxtx_control(mode_flags, lanes);
+ mdelay(1);
+ mtk_dsi_reset_dphy();
mtk_dsi_clk_hs_mode_disable();
mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
mtk_dsi_clk_hs_mode_enable();
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 9a00d1d149..3052689c90 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -115,6 +115,7 @@ enum {
enum {
DSI_RESET = BIT(0),
DSI_EN = BIT(1),
+ DPHY_RESET = BIT(2),
DSI_DUAL = BIT(4),
};