diff options
Diffstat (limited to 'src')
113 files changed, 5796 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig new file mode 100644 index 0000000000..343b30ba09 --- /dev/null +++ b/src/mainboard/google/zork/Kconfig @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_TREMBYLE + def_bool n + +config BOARD_GOOGLE_BASEBOARD_DALBOZ + def_bool n + +if BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_PICASSO + select VGA_BIOS + select BOARD_ROMSIZE_KB_16384 + select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL + select EC_GOOGLE_CHROMEEC_SKUID + select HAVE_ACPI_TABLES + select GFXUMA + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select MAINBOARD_HAS_CHROMEOS + select PICASSO_UART + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select HAVE_EM100_SUPPORT + select SYSTEM_TYPE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select HAVE_ACPI_RESUME + select DRIVERS_USB_ACPI + +config MAINBOARD_DIR + string + default google/zork + +config VARIANT_DIR + string + default "ezkinil" if BOARD_GOOGLE_EZKINIL + default "morphius" if BOARD_GOOGLE_MORPHIUS + default "trembyle" if BOARD_GOOGLE_TREMBYLE + default "dalboz" if BOARD_GOOGLE_DALBOZ + default "berknip" if BOARD_GOOGLE_BERKNIP + +config MAINBOARD_PART_NUMBER + string + default "Ezkinil" if BOARD_GOOGLE_EZKINIL + default "Morphius" if BOARD_GOOGLE_MORPHIUS + default "Trembyle" if BOARD_GOOGLE_TREMBYLE + default "Dalboz" if BOARD_GOOGLE_DALBOZ + default "Berknip" if BOARD_GOOGLE_BERKNIP + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_FAMILY + string + default "Google_Zork" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + +config AMD_FWM_POSITION_INDEX + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x03 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config USE_OEM_BIN + bool "Add an oem.bin file" + help + Add an oem.bin file to identify the manufacturer in SMBIOS, overriding the + CONFIG_MAINBOARD_SMBIOS_MANUFACTURER value. + +config OEM_BIN_FILE + string "OEM ID table" + depends on USE_OEM_BIN + default "" + +config VARIANT_HAS_FW_CONFIG + bool + help + Honor FW_CONFIG in CBI. + +config VARIANT_BOARD_VER_FW_CONFIG_VALID + int + default 256 + depends on VARIANT_HAS_FW_CONFIG + help + Which board version did FW_CONFIG become valid in CBI. + +endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name new file mode 100644 index 0000000000..065f60cb0a --- /dev/null +++ b/src/mainboard/google/zork/Kconfig.name @@ -0,0 +1,21 @@ +comment "Zork" + +config BOARD_GOOGLE_DALBOZ + bool "-> Dalboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_EZKINIL + bool "-> Ezkinil" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_MORPHIUS + bool "-> Morphius" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_TREMBYLE + bool "-> Trembyle" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE + +config BOARD_GOOGLE_BERKNIP + bool "-> Berknip" + select BOARD_GOOGLE_BASEBOARD_TREMBYLE diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc new file mode 100644 index 0000000000..07628c186b --- /dev/null +++ b/src/mainboard/google/zork/Makefile.inc @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += chromeos.c +romstage-y += ec.c +romstage-y += sku_id.c + +ramstage-y += chromeos.c +ramstage-y += ec.c +ramstage-y += sku_id.c + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += memlayout.ld +verstage-y += verstage.c +else +verstage-y += chromeos.c +verstage-y += ec.c +endif + +smm-y += smihandler.c + +subdirs-y += variants/baseboard +subdirs-y += spd + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include/baseboard/acpi + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/zork/board_info.txt b/src/mainboard/google/zork/board_info.txt new file mode 100644 index 0000000000..947c0420b1 --- /dev/null +++ b/src/mainboard/google/zork/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Trembyle +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c new file mode 100644 index 0000000000..0e7af52ecd --- /dev/null +++ b/src/mainboard/google/zork/bootblock.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <baseboard/variants.h> + +void bootblock_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/google/zork/chromeos.c b/src/mainboard/google/zork/chromeos.c new file mode 100644 index 0000000000..2256ef24b0 --- /dev/null +++ b/src/mainboard/google/zork/chromeos.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Write protect on zork is active low, so invert it here */ + return !gpio_get(CROS_WP_GPIO); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/zork/chromeos.fmd b/src/mainboard/google/zork/chromeos.fmd new file mode 100644 index 0000000000..963d1ee841 --- /dev/null +++ b/src/mainboard/google/zork/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xFF000000 0x1000000 { + SI_BIOS@0x0 0x1000000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RW_MRC_CACHE@0x0 0x10000 + MRC_CACHE_HOLE@0x10000 0x11000 + } + RW_SECTION_A@0x21000 0x39E000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x38DFC0 + RW_FWID_A@0x39DFC0 0x40 + } + RW_SECTION_B@0x3BF000 0x39E000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x38DFC0 + RW_FWID_B@0x39DFC0 0x40 + } + RW_ELOG(PRESERVE)@0x75D000 0x4000 + RW_SHARED@0x761000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x765000 0x2000 + RW_NVRAM(PRESERVE)@0x767000 0x5000 + RW_UNUSED@0x76C000 0x14000 + SMMSTORE(PRESERVE)@0x780000 0x20000 + RW_LEGACY(CBFS)@0x7A0000 0x360000 + WP_RO@0xB00000 0x500000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x4FC000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7C0 + GBB@0x1000 0x70000 + COREBOOT(CBFS)@0x71000 0x48B000 + } + } + } +} diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl new file mode 100644 index 0000000000..0831ddd5b7 --- /dev/null +++ b/src/mainboard/google/zork/dsdt.asl @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/ec.h> + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include <variant/acpi/mainboard.asl> + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include <variant/acpi/sleep.asl> + + /* Contains _SWS methods */ + #include <acpi_wake_source.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Thermal handler */ + #include <variant/acpi/thermal.asl> + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + /* ACPI code for EC I2C Audio Tunnel */ + #include <variant/acpi/audio.asl> + } +} +/* End of ASL file */ diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c new file mode 100644 index 0000000000..4c4329dd07 --- /dev/null +++ b/src/mainboard/google/zork/ec.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <soc/southbridge.h> +#include <variant/ec.h> + +static void ramstage_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} + +void mainboard_ec_init(void) +{ + if (ENV_RAMSTAGE) + ramstage_ec_init(); +} diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c new file mode 100644 index 0000000000..73ece65930 --- /dev/null +++ b/src/mainboard/google/zork/mainboard.c @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <string.h> +#include <console/console.h> +#include <cbfs.h> +#include <device/device.h> +#include <device/mmio.h> +#include <acpi/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <amdblocks/gpio_banks.h> +#include <cbmem.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <smbios.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/platform_descriptors.h> +#include <soc/southbridge.h> +#include <soc/smi.h> +#include <soc/soc_util.h> +#include <amdblocks/acpimmio.h> +#include <variant/ec.h> +#include <variant/thermal.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <commonlib/helpers.h> +#include <bootstate.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This table doesn't actually perform any routing. It only populates the + * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified + * in fch_apic_routing. The linux kernel only looks at this field as a backup + * if ACPI routing fails to describe the PCI routing correctly. The linux kernel + * also uses the APIC by default, so the value coded into the registers will be + * wrong. + * + * This table is also confusing because PCI Interrupt routing happens at the + * device/slot level, not the function level. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi + { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD + { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME + { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* + * This controls the device -> IRQ routing. + * The PIC values are limited to 0,1, 3 - 12, 14, 15. + */ +static const struct fch_apic_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} fch_pirq[] = { + { PIRQ_A, 6, 16 }, + { PIRQ_B, 6, 17 }, + { PIRQ_C, 14, 18 }, + { PIRQ_D, 15, 19 }, + { PIRQ_E, PIRQ_NC, PIRQ_NC }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, PIRQ_NC }, + { PIRQ_H, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQA, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQB, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQC, PIRQ_NC, PIRQ_NC }, + { PIRQ_SIRQD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_ASF, PIRQ_NC, PIRQ_NC }, + { PIRQ_PMON, PIRQ_NC, PIRQ_NC }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_CIR, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOA, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOB, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIOC, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, 5, 5 }, + { PIRQ_GPP0, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP1, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP2, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPP3, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C1, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C2, 10, 10 }, + { PIRQ_I2C3, 11, 11 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + { PIRQ_I2C4, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C5, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART2, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART3, PIRQ_NC, PIRQ_NC }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_apic_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(fch_pirq); i++) { + entry = fch_pirq + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + init_tables(); + + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + base_gpios = variant_base_gpio_table(&base_num_gpios); + override_gpios = variant_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, + override_num_gpios); +} + +static void mainboard_init(void *chip_info) +{ + const struct sci_source *gpes; + size_t num; + int boardid; + + mainboard_ec_init(); + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + mainboard_configure_gpios(); + + /* Update DUT configuration */ + variant_devtree_update(); + + /* + * Some platforms use SCI not generated by a GPIO pin (event above 23). + * For these boards, gpe_configure_sci() is still needed, but all GPIO + * generated events (23-0) must be removed from gpe_table[]. + * For boards that only have GPIO generated events, table gpe_table[] + * must be removed, and get_gpe_table() should return NULL. + */ + gpes = get_gpe_table(&num); + if (gpes != NULL) + gpe_configure_sci(gpes, num); +} + +void mainboard_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + variant_get_pcie_ddi_descriptors(pcie_descs, pcie_num, ddi_descs, ddi_num); +} + +/************************************************* + * Dedicated mainboard function + *************************************************/ +static void zork_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; +} + +static const struct soc_amd_gpio gpio_set_bl[] = { + PAD_GPO(GPIO_85, LOW), +}; + +static void reset_backlight_gpio(void *unused) +{ + printk(BIOS_DEBUG, "Reset backlight GPIO\n"); + /* Re-Enable backlight - GPIO 85 active low */ + /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ + program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ +} + +static void mainboard_final(void *chip_info) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + reset_backlight_gpio(NULL); + + if (gnvs) { + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + } +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = zork_enable, + .final = mainboard_final, +}; + +void __weak variant_devtree_update(void) +{ +} + +__weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + /* Default weak implementation - No overrides. */ + *size = 0; + return NULL; +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c new file mode 100644 index 0000000000..0e3b2da3c3 --- /dev/null +++ b/src/mainboard/google/zork/romstage.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <variant/ec.h> +#include <console/console.h> + +void __weak variant_romstage_entry(void) +{ + /* By default, don't do anything */ +} + +void mainboard_romstage_entry_s3(int s3_resume) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + gpios = variant_wifi_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + + mainboard_ec_init(); + + variant_romstage_entry(); +} diff --git a/src/mainboard/google/zork/sku_id.c b/src/mainboard/google/zork/sku_id.c new file mode 100644 index 0000000000..82ee355084 --- /dev/null +++ b/src/mainboard/google/zork/sku_id.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boardid.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint32_t sku_id(void) +{ + return google_chromeec_get_board_sku(); +} + +/* An unprovisioned SKU ID indicates we're in the factory booting prior to + proper SKU ID provisioning. */ +int boot_is_factory_unprovisioned(void) +{ + return sku_id() == CROS_SKU_UNPROVISIONED; +} diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c new file mode 100644 index 0000000000..7c88215ecb --- /dev/null +++ b/src/mainboard/google/zork/smihandler.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/smi.h> +#include <variant/ec.h> +#include <variant/gpio.h> +#include <console/console.h> + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_process_events(); +} +void mainboard_smi_sleep(u8 slp_typ) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..7ae89df525 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B4 EF +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..8d9fd4d9bf --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx1-4Bk-4BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 EF F6 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..af9ba32181 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-2BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 10 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 E7 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex new file mode 100644 index 0000000000..56677fa37a --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-2666-8Gbx2-4Bk-4BkG-16x10-8bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 10 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 55 24 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..cc1ca7384b --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 B3 E1 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex new file mode 100644 index 0000000000..3b1a73e7b8 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-16Gbx1-4Bk-2BkG-17x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 3C 41 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex new file mode 100644 index 0000000000..07342ab8fc --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-3200-8Gbx1-4Bk-2BkG-16x10-16bit.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 4C 24 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/DDR4-template.spd.hex b/src/mainboard/google/zork/spd/DDR4-template.spd.hex new file mode 100644 index 0000000000..6198f3daf1 --- /dev/null +++ b/src/mainboard/google/zork/spd/DDR4-template.spd.hex @@ -0,0 +1,336 @@ +# Generic DDR4 SPD template +# Fields that are not required should be set to zero +# CRC will be calculated when generating SPDs from this template, so no need +# to update here + +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization +01 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +00 + +# Connector to SDRAM Bit Mapping (DQ4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ8-11) +00 + +# Connector to SDRAM Bit Mapping (DQ12-15) +00 + +# Connector to SDRAM Bit Mapping (DQ16-19) +00 + +# Connector to SDRAM Bit Mapping (DQ20-23) +00 + +# Connector to SDRAM Bit Mapping (DQ24-27) +00 + +# Connector to SDRAM Bit Mapping (DQ28-31) +00 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +00 + +# Connector to SDRAM Bit Mapping (DQ36-39) +00 + +# Connector to SDRAM Bit Mapping (DQ40-43) +00 + +# Connector to SDRAM Bit Mapping (DQ44-47) +00 + +# Connector to SDRAM Bit Mapping (DQ48-51) +00 + +# Connector to SDRAM Bit Mapping (DQ52-55) +00 + +# Connector to SDRAM Bit Mapping (DQ56-59) +00 + +# Connector to SDRAM Bit Mapping (DQ60-63) +00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (blank) +00 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +00 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +00 + +# RC Extension, Module Nominal Height +00 + +# Module Maximum Thickness +00 + +# Reference Raw Card Used +00 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +00 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (blank) +00 + +# Module Manufacturer's ID Code, MSB (blank) +00 + +# Module Manufacturing Location (blank) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (blank) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (blank) +00 + +# DRAM Manufacturer's ID code, MSB (blank) +00 + +# DRAM Stepping (Undefined) +00 + +# Module Manufacturer's Specific Data (blank) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc new file mode 100644 index 0000000000..e401fa6fdc --- /dev/null +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This directory +SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# TODO: Remove channel suffix when b:141434940 is fixed +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001 +APCB_SOURCES += empty # 0b0010 +APCB_SOURCES += empty # 0b0011 +APCB_SOURCES += empty # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/spd/empty.spd.hex b/src/mainboard/google/zork/spd/empty.spd.hex new file mode 100644 index 0000000000..0d22dd0cf0 --- /dev/null +++ b/src/mainboard/google/zork/spd/empty.spd.hex @@ -0,0 +1,33 @@ +#Empty SPD - placeholder file +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex new file mode 100644 index 0000000000..1c5e87f9d4 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NCJR-VKC.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx16) +02 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +87 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +2E + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (C0) +02 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +C0 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +E2 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (H5AN8G6NCJR-VKC ) +48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20 +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex new file mode 100644 index 0000000000..144c8e3f08 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5AN8G6NDJR-XNC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5AN8G6NDJR-XNC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36 +4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex new file mode 100644 index 0000000000..e75e4c12d9 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-VKC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-VKC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex new file mode 100644 index 0000000000..3cfb32cfc8 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-H5ANAG6NCMR-XNC.spd.hex @@ -0,0 +1,33 @@ +# Hynix H5ANAG6NCMR-XNC +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex new file mode 100644 index 0000000000..7ad9466cf4 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-HMA851S6CJR6N-VK.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (Flipchip SDP) +00 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx16) +02 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +87 + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +2E + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (C0) +02 + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +C0 + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +E2 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (HMA851S6CJR6N-VK ) +48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex new file mode 100644 index 0000000000..ff166d6e75 --- /dev/null +++ b/src/mainboard/google/zork/spd/hynix-HMAA1GS6CMR6N-VK.spd.hex @@ -0,0 +1,331 @@ +# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512) +23 + +# SPD Revision (Rev. 1.1) +11 + +# Key Byte / DRAM Device Type (DDR4 SDRAM) +0C + +# Key Byte / Module Type (nECC SO-DIMM) +03 + +# SDRAM Density and Banks (2BG/4BK/8Gb) +45 + +# SDRAM Addressing (16/10) +21 + +# Primary SDRAM Package Type (DDP) +91 + +# SDRAM Optional Features (Unlimited MAC) +08 + +# SDRAM Thermal and Refresh Options (Reserved) +00 + +# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported) +60 + +# Secondary SDRAM Package Type +00 + +# Module Nominal Volatage, VDD (1.2V) +03 + +# Module Organization (1Rx8) +01 + +# Module Memory Bus Width (LP/x64) +03 + +# Module Thermal Sensor (Termal sensor not incorporated) +00 + +# Extended Module Type (Reserved) +00 + +# Reserved +00 + +# Timebases (MTB : 125ps, FTB : 1ps) +00 + +# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns) +06 + +# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns) +0D + +# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14) +F8 + +# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20) +3F + +# CAS Latencies Supported, Third Byte +00 + +# CAS Latencies Supported, Fourth Byte +00 + +# Minimum CAS Latency Time (tAAmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns) +6E + +# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns) +6E + +# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns) +11 + +# tRASmin, Least Significant Byte (32ns) +00 + +# tRCmin, Least Significant Byte (45.75ns) +6E + +# tRFC1min, LSB (350ns) +F0 + +# tRFC1min, MSB (350ns) +0A + +# tRFC2min, LSB (260ns) +20 + +# tRFC2min, MSB (260ns) +08 + +# tRFC4min, LSB (160ns) +00 + +# tRFC4min, MSB (160ns) +05 + +# Upper Nibble for tFAW (30ns) +00 + +# tFAWmin LSB (30ns) +F0 + +# tRRD_Smin (5.3ns) +2B + +# tRRD_L min (6.40ns) +34 + +# tCCD_Lmin, same bank group (5ns) +28 + +# tWRmin Upper Nibbles (15ns) +00 + +# tWRmin (15ns) +78 + +# tWTRmin Upper Nibbles (2.5ns/7.5ns) +00 + +# tWTR_Smin (2.5ns) +14 + +# tWTR_Lmin (7.5ns) +3C + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Connector to SDRAM Bit Mapping (DQ0-3) +16 + +# Connector to SDRAM Bit Mapping (DQ4-7) +36 + +# Connector to SDRAM Bit Mapping (DQ8-11) +0B + +# Connector to SDRAM Bit Mapping (DQ12-15) +35 + +# Connector to SDRAM Bit Mapping (DQ16-19) +16 + +# Connector to SDRAM Bit Mapping (DQ20-23) +36 + +# Connector to SDRAM Bit Mapping (DQ24-27) +0B + +# Connector to SDRAM Bit Mapping (DQ28-31) +35 + +# Connector to SDRAM Bit Mapping (CB0-3) +00 + +# Connector to SDRAM Bit Mapping (CB4-7) +00 + +# Connector to SDRAM Bit Mapping (DQ32-35) +16 + +# Connector to SDRAM Bit Mapping (DQ36-39) +36 + +# Connector to SDRAM Bit Mapping (DQ40-43) +0B + +# Connector to SDRAM Bit Mapping (DQ44-47) +35 + +# Connector to SDRAM Bit Mapping (DQ48-51) +16 + +# Connector to SDRAM Bit Mapping (DQ52-55) +36 + +# Connector to SDRAM Bit Mapping (DQ56-59) +0B + +# Connector to SDRAM Bit Mapping (DQ60-63) +35 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 + +# Fine offset for tCCD_Lmin, same bank group (5ns) +00 + +# tRRD_L min offset (6.40ns) +9C + +# tRRD_Smin offset (5.3ns) +B5 + +# Fine offset for tRCmin (45.75ns) +00 + +# Fine offset for tRPmin (13.75ns) +00 + +# Fine offset for tRCDmin (13.75ns) +00 + +# Fine offset for tAAmin (13.75ns) +00 + +# Fine offset for tCKAVGmax (1.6ns) +E7 + +# Fine offset for tCKAVGmin (0.75ns) +00 + +# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte) +FD + +# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte) +EE + +# RC Extention, Module Nominal Height (30.00) +0F + +# Module Maximum Thickness (1.0/1.2) +01 + +# Reference Raw Card Used (ZZ0) +1F + +# Address Mapping from Edge Connector to DRAM (Standard) +00 + +# Reserved +00 00 00 00 00 00 00 00 + +# Reserved (Must be coded as 0x00) +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 + +# CRC for Module Specific Section, LSB (CRC cover 128~253 byte) +7D + +# CRC for Module Specific Section, MSB (CRC cover 128~253 byte) +21 + +# Reserved +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +# Module Manufacturer's ID Code, LSB (SK hynix) +80 + +# Module Manufacturer's ID Code, MSB (SK hynix) +AD + +# Module Manufacturing Location (SK hynix (Icheon)) +01 + +# Module Manufacturing Date (Variable) +00 + +# Module Manufacturing Date (Variable) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Serial Number (Undefined) +00 + +# Module Part Number (HMAA1GS6CMR6N-VK ) +48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B +20 20 20 20 + +# Module Revision Code (Revision 0) +00 + +# DRAM Manufacturer's ID code, LSB (SK hynix) +80 + +# DRAM Manufacturer's ID code, MSB (SK hynix) +AD + +# DRAM Stepping (Undefined) +FF + +# Module Manufacturer's Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 DD + +# Reserved +00 00 + +# End User Programmable +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000000..17778473af --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex new file mode 100644 index 0000000000..988ea54b23 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A1G16KNR-075-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KNR-075:E +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex new file mode 100644 index 0000000000..67640fe849 --- /dev/null +++ b/src/mainboard/google/zork/spd/micron-MT40A512M16TB-062E-J.spd.hex @@ -0,0 +1,33 @@ +# MT40A512M16TB-062E:J +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31 +32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex new file mode 100644 index 0000000000..e16d2f729b --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4A8G165WC-BCTD +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000000..4fb1561c6a --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4A8G165WC-BCWE +23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex new file mode 100644 index 0000000000..390e5a5417 --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WA-BCWE.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WA-BCWE +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex new file mode 100644 index 0000000000..ede001a4d5 --- /dev/null +++ b/src/mainboard/google/zork/spd/samsung-K4AAG165WB-MCTD.spd.hex @@ -0,0 +1,33 @@ +# Samsung K4AAG165WB-MCTD +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B +34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..4bcaf68aed --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +bootblock-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +endif +verstage-y += tpm_tis.c + +romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +romstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +romstage-y += tpm_tis.c + +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += fsps_baseboard_trembyle.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c +ramstage-y += helpers.c +ramstage-y += tpm_tis.c + +# Add OEM ID table +ifeq ($(CONFIG_USE_OEM_BIN),y) +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw +endif #($(CONFIG_USE_OEM_BIN),y) + +# APCB Board ID GPIO configuration. +# These GPIOs determine which memory SPD will be used during boot. +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y) +APCB_BOARD_ID_GPIO0 = 132 1 0 +APCB_BOARD_ID_GPIO1 = 90 1 0 +APCB_BOARD_ID_GPIO2 = 86 3 0 +APCB_BOARD_ID_GPIO3 = 69 1 0 +else +$(error Undefined APCB selection GPIOS for Zork baseboard) +endif #($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..c90c3225a3 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c new file mode 100644 index 0000000000..e67755ccc5 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/bsd/compiler.h> + +void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +static const picasso_fsp_pcie_descriptor pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = NVME_START_LANE, + .end_lane = NVME_END_LANE, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + .clk_pm_support = true, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = WLAN_START_LANE, + .end_lane = WLAN_END_LANE, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = SD_START_LANE, + .end_lane = SD_END_LANE, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +{ + *num = ARRAY_SIZE(pcie_descriptors); + return pcie_descriptors; +} + +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Different configurations of dalboz have different ddi configurations. + * Therefore, don't provide any baseboard defaults. */ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c new file mode 100644 index 0000000000..fb96ff2537 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/bsd/compiler.h> +#include <soc/soc_util.h> + +void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some + * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. + * Those parts need to be configured as Type 2. */ + +static const picasso_fsp_pcie_descriptor pco_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 3, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +static const picasso_fsp_pcie_descriptor dali_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = NVME_START_LANE, + .end_lane = NVME_END_LANE, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + .clk_pm_support = true, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = WLAN_START_LANE, + .end_lane = WLAN_END_LANE, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = SD_START_LANE, + .end_lane = SD_END_LANE, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_pcie_descriptors); + return dali_pcie_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_pcie_descriptors); + return pco_pcie_descriptors; + } + +} + +static const picasso_fsp_ddi_descriptor pco_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT1 HDMI + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP2, DB OPT1 USB-C1 + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { + // DDI3, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const picasso_fsp_ddi_descriptor dali_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_ddi_descriptors); + return dali_ddi_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_ddi_descriptors); + return pco_ddi_descriptors; + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c new file mode 100644 index 0000000000..b5b2847841 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <soc/smi.h> +#include <stdlib.h> +#include <boardid.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_rom[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* PEN_POWER_EN - reset */ + PAD_GPO(GPIO_5, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_GPI(GPIO_24, PULL_UP), + PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + /* PCIE_RST0_L - Fixed timings */ + /* TODO: Make sure this gets locked at end of post */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L - Variable timings (May remove) */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_TOUCHPAD_PS2 - reset */ + PAD_GPO(GPIO_67, LOW), + /* EMMC_RESET - reset (default stuffing unused)*/ + PAD_GPO(GPIO_68, HIGH), + /* EN_PWR_CAMERA - reset */ + PAD_GPO(GPIO_76, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* CLK_REQ2_L - NVMe */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* USI_RESET - reset */ + PAD_GPO(GPIO_140, HIGH), + /* USB_HUB_RST_L - reset*/ + PAD_GPO(GPIO_141, LOW), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_wifi[] = { + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* PCIE_WAKE_L */ + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + /* PEN_DETECT_ODL */ + PAD_GPI(GPIO_4, PULL_UP), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* DMIC_SEL */ + PAD_GPO(GPIO_6, LOW), // Select Camera 1 Dmic + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + /* TODO: Make sure driver sets as wake source */ + PAD_GPI(GPIO_9, PULL_UP), + /* S0iX SLP - (unused - goes to EC & FPMCU */ + PAD_GPI(GPIO_10, PULL_UP), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_11, PULL_UP), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_UP), + /* DMIC_SEL */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), + /* USB_OC1_L - USB C1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_UP), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_UP), + /* */ + PAD_GPI(GPIO_32, PULL_DOWN), + /* EN_PWR_TOUCHPAD_PS2 */ + /* + * EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before + * using this GPIO. Otherwise SPI flash access will be very slow. + */ + PAD_GPO(GPIO_67, HIGH), + /* EMMC_RESET */ + PAD_GPO(GPIO_68, LOW), + /* RAM ID 3*/ + PAD_GPI(GPIO_69, PULL_NONE), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* UNUSED */ + PAD_GPO(GPIO_84, HIGH), + /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ + PAD_GPO(GPIO_85, HIGH), + /* RAM ID 2 */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* RAM ID 1 */ + PAD_GPI(GPIO_90, PULL_NONE), + /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + PAD_GPO(GPIO_91, LOW), + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_UP), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_UP), + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), + /* RAM ID 0 */ + PAD_GPI(GPIO_132, PULL_NONE), + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, LOW), + /* USB_HUB_RST_L */ + PAD_GPO(GPIO_141, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_143, LOW), + /* + * USI_REPORT_EN - TODO: Driver resets this later. + * Do we want it high or low initially? + */ + PAD_GPO(GPIO_144, HIGH), +}; + +const __weak +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const __weak +struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_rom); + return gpio_set_stage_rom; +} + +const __weak +struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_wifi); + return gpio_set_wifi; +} + +const __weak +struct soc_amd_gpio *variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +/* + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. + */ +const __weak struct sci_source *get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c new file mode 100644 index 0000000000..6101330a79 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <soc/smi.h> +#include <stdlib.h> +#include <boardid.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_rom[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_UP, EDGE_LOW, STATUS), + /* PEN_POWER_EN - reset */ + PAD_GPO(GPIO_5, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_GPI(GPIO_24, PULL_UP), + PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + /* PCIE_RST0_L - Fixed timings */ + /* TODO: Make sure this gets locked at end of post */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L - Variable timings (May remove) */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_TOUCHPAD_PS2 - reset */ + PAD_GPO(GPIO_67, LOW), + /* EMMC_RESET - reset (default stuffing unused)*/ + PAD_GPO(GPIO_68, HIGH), + /* EN_PWR_CAMERA - reset */ + PAD_GPO(GPIO_76, LOW), + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), + /* ESPI_ALERT_L (may be unused) */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* USI_RESET - reset */ + PAD_GPO(GPIO_140, HIGH), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_wifi[] = { + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* PCIE_WAKE_L */ + PAD_NF(GPIO_2, WAKE_L, PULL_UP), + /* PEN_DETECT_ODL */ + PAD_GPI(GPIO_4, PULL_UP), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* FPMCU_INT_L */ + PAD_GPI(GPIO_6, PULL_UP), + PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5), + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + /* TODO: Make sure driver sets as wake source */ + PAD_GPI(GPIO_9, PULL_UP), + /* S0iX SLP - (unused - goes to EC & FPMCU */ + PAD_GPI(GPIO_10, PULL_UP), + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, HIGH), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_UP), + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* BT_DISABLE */ + PAD_GPO(GPIO_14, LOW), + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), + /* USB_OC1_L - USB C1 + USB A1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_UP), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_UP), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, HIGH), + /* EN_PWR_TOUCHPAD_PS2 */ + /* + * EN_PWR_TOUCHPAD_PS2 - Make sure Ext ROM Sharing is disabled before + * using this GPIO. Otherwise SPI flash access will be very slow. + */ + PAD_GPO(GPIO_67, HIGH), + /* EMMC_RESET */ + PAD_GPO(GPIO_68, LOW), + /* FPMCU_BOOT0 - TODO: Check this */ + PAD_GPO(GPIO_69, LOW), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ + PAD_GPO(GPIO_85, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), + /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */ + PAD_GPO(GPIO_91, LOW), + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_UP), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_UP), + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_UP), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_UP), + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, LOW), + /* UART1_RXD - FPMCU */ + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* UART1_TXD - FPMCU */ + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + /* USI_REPORT_EN */ + /* TODO: Driver resets this later. Do we want it high or low initially? */ + PAD_GPO(GPIO_144, HIGH), +}; + +const __weak +struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const __weak +struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_rom); + return gpio_set_stage_rom; +} + +const __weak +struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_wifi); + return gpio_set_wifi; +} + +const __weak +struct soc_amd_gpio *variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +/* + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. + */ +const __weak struct sci_source *get_gpe_table(size_t *num) +{ + return NULL; +} diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c new file mode 100644 index 0000000000..06cc9ad4ff --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/helpers.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <inttypes.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +/* Global definitions for FW_CONFIG values */ +enum { + /* Daughterboard index for attributes. */ + FW_CONFIG_MASK_DB_INDEX = 0xf, + FW_CONFIG_DB_INDEX_SHIFT = 0, + /* Mainboard USB index for attributes. */ + FW_CONFIG_MASK_MB_USB_INDEX = 0xf, + FW_CONFIG_MB_USB_INDEX_SHIFT = 4, + /* Lid accelerometer properties. */ + FW_CONFIG_MASK_LID_ACCEL = 0x7, + FW_CONFIG_LID_ACCEL_SHIFT = 8, + /* Base gyro sensor properties. */ + FW_CONFIG_MASK_BASE_GYRO = 0x7, + FW_CONFIG_BASE_GYRO_SHIFT = 11, + /* Keyboard backlight presence */ + FW_CONFIG_MASK_KEYB_BL = 0x1, + FW_CONFIG_KEYB_BL_SHIFT = 14, + /* Tablet mode supported through lid angle */ + FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE = 0x1, + FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT = 15, + /* Stylus presence */ + FW_CONFIG_MASK_STYLUS = 0x1, + FW_CONFIG_STYLUS_SHIFT = 16, + /* Fingerprint sensor presence */ + FW_CONFIG_MASK_FP = 0x1, + FW_CONFIG_SHIFT_FP = 17, + /* NVME presence */ + FW_CONFIG_MASK_NVME = 0x1, + FW_CONFIG_SHIFT_NVME = 18, + /* EMMC presence */ + FW_CONFIG_MASK_EMMC = 0x1, + FW_CONFIG_SHIFT_EMMC = 19, + /* SD controller type */ + FW_CONFIG_MASK_SD_CTRLR = 0x7, + FW_CONFIG_SHIFT_SD_CTRLR = 20, + /* SPI speed value */ + FW_CONFIG_MASK_SPI_SPEED = 0xf, + FW_CONFIG_SHIFT_SPI_SPEED = 23, + /* Fan information */ + FW_CONFIG_MASK_FAN = 0x3, + FW_CONFIG_SHIFT_FAN = 27, +}; + +int variant_fw_config_valid(void) +{ + static uint32_t board_version; + const uint32_t bv_valid = CONFIG_VARIANT_BOARD_VER_FW_CONFIG_VALID; + + if (!CONFIG(VARIANT_HAS_FW_CONFIG)) + return 0; + + /* Fast path for non-zero board version. */ + if (board_version >= bv_valid) + return 1; + + if (google_chromeec_cbi_get_board_version(&board_version)) { + printk(BIOS_ERR, "Unable to obtain board version for FW_CONFIG\n"); + return 0; + } + + if (board_version >= bv_valid) + return 1; + + return 0; +} + +static int get_fw_config(uint32_t *val) +{ + static uint32_t known_value; + + if (!variant_fw_config_valid()) + return -1; + + if (known_value) { + *val = known_value; + return 0; + } + + if (google_chromeec_cbi_get_fw_config(&known_value)) { + printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); + return -1; + } + + *val = known_value; + + return 0; +} + +static unsigned int extract_field(uint32_t mask, int shift) +{ + uint32_t fw_config; + + /* On errors nothing is assumed to be set. */ + if (get_fw_config(&fw_config)) + return 0; + + return (fw_config >> shift) & mask; +} + +int variant_has_emmc(void) +{ + return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC); +} + +int variant_has_nvme(void) +{ + return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME); +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl new file mode 100644 index 0000000000..ae5663e7c7 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (EC0.CREC) { + #include <ec/google/chromeec/acpi/codec.asl> +} + +/* machine driver */ +Device (I2SM) +{ + Name (_HID, "AMDI5682") + Name (_UID, 1) + Name (_DDN, "I2S machine Driver") + + Name (_CRS, ResourceTemplate () + { +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) + /* DMIC select GPIO */ + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionNone, "\\_SB.GPIO", 0x00, + ResourceConsumer,,) { 6 } +#else + /* DMIC select GPIO */ + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionNone, "\\_SB.GPIO", 0x00, + ResourceConsumer,,) { 13 } +#endif + }) + /* Device-Specific Data */ + Name (_DSD, Package () + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () + { + "dmic-gpio", Package () { ^I2SM, 0, 0, 0 } + } + } + + }) + Method (_STA) + { + Return (0xF) + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl new file mode 100644 index 0000000000..b3d39969f1 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl new file mode 100644 index 0000000000..21c31a3b01 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sb_fch.asl @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/gpio.h> +#include <soc/iomap.h> + +Device (AAHB) +{ + Name (_HID, "AAHB0000") + Name (_UID, 0x0) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (GPIO) +{ + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) + + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IGPI + } Else { + IRQN=PGPI + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (MMC0) +{ + Name (_HID, "AMDI0040") + Name (_UID, 0x0) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IMMC + } Else { + IRQN=PMMC + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_EMMC_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR0) +{ + Name (_HID, "AMD0020") + Name (_UID, 0x0) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IUA0 + } Else { + IRQN=PUA0 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (FUR1) { + Name (_HID, "AMD0020") + Name (_UID, 0x1) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=IUA1 + } Else { + IRQN=PUA1 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C2) { + Name (_HID, "AMD0010") + Name (_UID, 0x2) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=II22 + } Else { + IRQN=PI22 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C3) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x3) + Method(_CRS ,0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If(PMOD) { + IRQN=II23 + } Else { + IRQN=PI23 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (MISC) +{ + Name (_HID, "AMD0040") + Name (_UID, 0x3) + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl new file mode 100644 index 0000000000..c8fb05fe1f --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/sleep.asl @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl new file mode 100644 index 0000000000..8f5aa6ab5e --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/thermal.h> + +/* Thermal Zone */ + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + /* Thermal constants for passive cooling */ + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 2 seconds */ + Name (_TSP, 20) + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Threshold for OS to shutdown */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Threshold for passive cooling */ + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + /* Processors used for passive cooling */ + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + /* Get temperature from EC in deci-kelvin */ + Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + + /* Critical temperature in deci-kelvin */ + Store (CTOK (\TCRT), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + /* Wait 1 second for EC to re-poll */ + Sleep (1000) + + /* Re-read temperature from EC */ + Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + } +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..8ef0645afd --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable LID switch */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ IRQ (Level, ActiveHigh, Exclusive) {1} +#define SIO_EC_PS2M_IRQ IRQ (Level, ActiveHigh, Exclusive) {12} + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#endif diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..4801a5ec7b --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#ifndef __ACPI__ +#include <soc/gpio.h> +#include <platform_descriptors.h> + +#define H1_PCH_INT GPIO_3 +#define PEN_DETECT_ODL GPIO_4 +#define PEN_POWER_EN GPIO_5 +#define TOUCHPAD_INT_ODL GPIO_9 +#define EC_FCH_WAKE_L GPIO_24 +#define WIFI_PCIE_RESET_L GPIO_26 +#define PCIE_RST1_L GPIO_27 +#define EN_PWR_WIFI GPIO_29 +#define NVME_AUX_RESET_L GPIO_40 +#define WIFI_AUX_RESET_L GPIO_42 +#define EN_PWR_CAMERA GPIO_76 +#define EN_PWR_TOUCHPAD_PS2 GPIO_67 +#define PCIE_0_WIFI_CLKREQ_ODL GPIO_92 +#define PCIE_1_SD_CLKREQ_ODL GPIO_115 +#define BIOS_FLASH_WP_ODL GPIO_137 +#define SD_AUX_RESET_L GPIO_142 +#define WLAN_CLKREQ CLK_REQ0 +#define SD_CLKREQ CLK_REQ1 + +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) +#define NVME_START_LANE 4 +#define NVME_END_LANE 5 +#define WLAN_START_LANE 0 +#define WLAN_END_LANE 0 +#define SD_START_LANE 1 +#define SD_END_LANE 1 +#else +#define NVME_START_LANE 0 +#define NVME_END_LANE 1 +#define WLAN_START_LANE 4 +#define WLAN_END_LANE 4 +#define SD_START_LANE 5 +#define SD_END_LANE 5 +#endif + +#if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) +#define FPMCU_INT_L GPIO_6 +#define FPMCU_RST_ODL GPIO_11 +#define EC_IN_RW_OD GPIO_130 +#define PCIE_4_NVME_CLKREQ_ODL GPIO_132 +#define NVME_CLKREQ CLK_REQ4 +#else +#define EC_IN_RW_OD GPIO_11 +#define PCIE_2_NVME_CLKREQ_ODL GPIO_116 +#define NVME_CLKREQ CLK_REQ2 +#endif + +/* SPI Write protect */ +#define CROS_WP_GPIO BIOS_FLASH_WP_ODL +#define GPIO_EC_IN_RW EC_IN_RW_OD + +/* PCIe reset pins */ +#define PCIE_0_RST WIFI_AUX_RESET_L +#define PCIE_1_RST SD_AUX_RESET_L +#define PCIE_2_RST 0 +#define PCIE_3_RST 0 +#define PCIE_4_RST NVME_AUX_RESET_L + +#endif /* _ACPI__ */ + +/* These define the GPE, not the GPIO. */ +#define EC_SCI_GPI 3 /* eSPI system event -> GPE 3 */ +#define EC_WAKE_GPI 15 /* AGPIO 24 -> GPE 15 */ + +/* EC sync irq */ +#define EC_SYNC_IRQ 31 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h new file mode 100644 index 0000000000..b3c951bbaf --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/thermal.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Picasso Thermal Requirements + * TDP (W) 15 + * T die,max (°C) 105 + * T ctl,max 105 + * T die,lmt (default) 100 + * T ctl,lmt (default) 100 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +#endif diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..c682eca1a4 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <stddef.h> +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <soc/platform_descriptors.h> +#include "chip.h" + +const struct sci_source *get_gpe_table(size_t *num); +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size); +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size); +/* + * This function provides base GPIO configuration table. It is typically provided by + * baseboard using a weak implementation. If GPIO configuration for a variant differs + * significantly from the baseboard, then the variant can also provide a strong implementation + * of this function. + */ +const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by variant_base_gpio_table(). + */ +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); +void variant_romstage_entry(void); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + +/* Per variant FSP-S initialization, default implementation in baseboard and + * overrideable by the variant. */ +void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num); + +/* Provide the descriptors for the associated baseboard for the variant. These functions + * can be used for obtaining the baseboard's descriptors if the variant followed the + * baseboard. */ +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num); +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); + +/* Retrieve attributes from FW_CONFIG in CBI. */ +/* Return 1 if FW_CONFIG expected to be valid, else 0. */ +int variant_fw_config_valid(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_emmc(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_nvme(void); + +/* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ +int boot_is_factory_unprovisioned(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/baseboard/tpm_tis.c b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000000..52e83cf44c --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <security/tpm/tis.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(H1_PCH_INT); +} diff --git a/src/mainboard/google/zork/variants/berknip/Makefile.inc b/src/mainboard/google/zork/variants/berknip/Makefile.inc new file mode 100644 index 0000000000..b1212bcbdd --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += ./romstage.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/berknip/gpio.c b/src/mainboard/google/zork/variants/berknip/gpio.c new file mode 100644 index 0000000000..f7a1e37e06 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/gpio.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +static const struct soc_amd_gpio berknip_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(berknip_v1_gpio_set_stage_ram); + return berknip_v1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/ec.h b/src/mainboard/google/zork/variants/berknip/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h b/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h b/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb new file mode 100644 index 0000000000..fe83307954 --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "3" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "25000" #mw + register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "25000" #mw + + register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/berknip/romstage.c b/src/mainboard/google/zork/variants/berknip/romstage.c new file mode 100644 index 0000000000..6d93b5e91e --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/romstage.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void variant_romstage_entry(void) +{ + /* Power the wifi card */ + gpio_set(EN_PWR_WIFI, 1); +} + +static const struct soc_amd_gpio berknip_gpio_set_wifi[] = { + /* EN_PWR_WIFI - Power off. Pull high in romstage.c */ + PAD_GPO(GPIO_29, LOW), +}; + +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(berknip_gpio_set_wifi); + return berknip_gpio_set_wifi; +} diff --git a/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc new file mode 100644 index 0000000000..7731c0733b --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/spd/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = samsung-K4A8G165WC-BCTD_x2 # 0b0000 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b0001 +# b/149596178: We can't use dual channel channel until the PSP supports missing +# channels. +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc new file mode 100644 index 0000000000..a616e2fdc0 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += romstage.c + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c new file mode 100644 index 0000000000..3e705a6b34 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/gpio.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +/* This table is used by dalboz variant with board version < 2. */ +static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* USB_OC2_L - USB A0 & A1 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* Unused */ + PAD_GPI(GPIO_143, PULL_DOWN), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); + return bid_1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb new file mode 100644 index 0000000000..8ac3348e2a --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "6000" #mw + register "fast_ppt_limit" = "9000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "2500" #second + register "sustained_power_limit" = "4800" #mw + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # I2C3 for H1 + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + end + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "120" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c new file mode 100644 index 0000000000..42e36c4525 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void variant_romstage_entry(void) +{ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version < 2) { + /* SET PCIE_RST0_L HIGH */ + gpio_set(WIFI_PCIE_RESET_L, 1); + } else { + /* SET PCIE_RST1_L HIGH */ + gpio_set(PCIE_RST1_L, 1); + } +} diff --git a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc new file mode 100644 index 0000000000..7baf8be205 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001 +APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010 +APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c new file mode 100644 index 0000000000..aae8f03058 --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/variant.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/device.h> +#include <drivers/i2c/generic/chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/i2c_tunnel/chip.h> +#include <string.h> + +#define EC_PNP_ID 0x0c09 + +/* Look for an EC device of type PNP with id 0x0c09 */ +static bool match_ec_dev(DEVTREE_CONST struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PNP) + return false; + + if (dev->path.pnp.port != EC_PNP_ID) + return false; + + return true; +} + +extern struct chip_operations drivers_i2c_generic_ops; + +/* Look for an I2C device with HID "10EC5682" */ +static bool match_audio_dev(DEVTREE_CONST struct device *dev) +{ + struct drivers_i2c_generic_config *cfg; + + if (dev->chip_ops != &drivers_i2c_generic_ops) + return false; + + cfg = dev->chip_info; + + return !strcmp(cfg->hid, "10EC5682"); +} + +extern struct chip_operations ec_google_chromeec_i2c_tunnel_ops; + +/* Look for Cros EC tunnel device which has audio device under it. */ +static bool match_audio_tunnel(DEVTREE_CONST struct device *dev) +{ + const struct device *audio_dev; + + if (dev->chip_ops != &ec_google_chromeec_i2c_tunnel_ops) + return false; + + audio_dev = dev_find_matching_device_on_bus(dev->link_list, match_audio_dev); + + if (!audio_dev) + return false; + + return true; +} + +/* + * This is to allow support for audio on older board versions (< 2). [b/153458561]. This + * should be removed once these boards are phased out. + */ +static void update_audio_configuration(void) +{ + uint32_t board_version; + const struct device *lpc_controller; + const struct device *ec_dev; + const struct device *i2c_tunnel_dev; + struct ec_google_chromeec_i2c_tunnel_config *cfg; + + /* If CBI board version cannot be read, assume this is an older revision of hardware. */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version >= 2) + return; + + lpc_controller = SOC_LPC_DEV; + if (lpc_controller == NULL) { + printk(BIOS_ERR, "%s: LPC controller device not found!\n", __func__); + return; + } + + ec_dev = dev_find_matching_device_on_bus(lpc_controller->link_list, match_ec_dev); + + if (ec_dev == NULL) { + printk(BIOS_ERR, "%s: EC device not found!\n", __func__); + return; + } + + i2c_tunnel_dev = dev_find_matching_device_on_bus(ec_dev->link_list, match_audio_tunnel); + + if (i2c_tunnel_dev == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device not found!\n", __func__); + return; + } + + cfg = i2c_tunnel_dev->chip_info; + if (cfg == NULL) { + printk(BIOS_ERR, "%s: I2C tunnel device config not found!\n", __func__); + return; + } + + cfg->remote_bus = 5; +} + +static int sku_has_emmc(void) +{ + uint32_t board_sku = sku_id(); + + /* Factory flow requires all OS boot media to be enabled. */ + if (boot_is_factory_unprovisioned()) + return 1; + + /* FIXME: This needs to be fw_config controlled. */ + /* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */ + if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN) + return 1; + + return 0; +} + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + if (sku_has_emmc()) { + if (sku_id() == 0x5A800003) + /* rev0 boards have issues with HS400 */ + cfg->sd_emmc_config = SD_EMMC_EMMC_HS200; + } else { + cfg->sd_emmc_config = SD_EMMC_DISABLE; + } + + update_audio_configuration(); +} + +/* FIXME: Comments seem to suggest these are not entirely correct. */ +static const picasso_fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DP2 pins not connected on Dali + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const picasso_fsp_ddi_descriptor hdmi_ddi_descriptors[] = { + { // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + // DP2 pins not connected on Dali + { // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + uint32_t board_sku = sku_id(); + + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + + /* SKU 1, A, and D DB have HDMI, as well as unknown */ + /* FIXME: this needs to be fw_config controlled. */ + if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001) + || (board_sku == CROS_SKU_UNKNOWN)) { + *ddi_descs = &hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); + } else { + *ddi_descs = &non_hdmi_ddi_descriptors[0]; + *ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors); + } +} diff --git a/src/mainboard/google/zork/variants/ezkinil/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/Makefile.inc new file mode 100644 index 0000000000..51d19fe9ba --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/Makefile.inc @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c new file mode 100644 index 0000000000..1b1ed54447 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> +static const struct soc_amd_gpio ezkinil_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(ezkinil_v1_gpio_set_stage_ram); + return ezkinil_v1_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h b/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb new file mode 100644 index 0000000000..c208dae9ca --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "20000" #mw + register "fast_ppt_limit" = "24000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "12000" #mw + + register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc new file mode 100644 index 0000000000..cd912726c4 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/spd/Makefile.inc @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x2 # 0b0000 +APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010 +APCB_SOURCES += micron-MT40A1G16KNR-075-E_x2 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCTD_x2 # 0b0100 +APCB_SOURCES += empty # 0b0101 +APCB_SOURCES += empty # 0b0110 +APCB_SOURCES += empty # 0b0111 +APCB_SOURCES += empty # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 +APCB_SOURCES += empty # 0b1111 diff --git a/src/mainboard/google/zork/variants/ezkinil/variant.c b/src/mainboard/google/zork/variants/ezkinil/variant.c new file mode 100644 index 0000000000..d7cf5a8803 --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/variant.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> + +static int sku_has_emmc(void) +{ + uint32_t board_sku = sku_id(); + + /* Factory flow requires all OS boot media to be enabled. */ + if (boot_is_factory_unprovisioned()) + return 1; + + if ((board_sku == 0x5A020000) || + (board_sku == 0x5A020001) || (board_sku == 0x5A020002) || + (board_sku == 0x5A020005) || (board_sku == 0x5A020006) || + (board_sku == 0x5A020009) || (board_sku == 0x5A02000A) || + (board_sku == 0x5A02000D) || (board_sku == 0x5A02000E)) + return 1; + + return 0; +} + +void variant_devtree_update(void) +{ + struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + if (!sku_has_emmc()) + cfg->sd_emmc_config = SD_EMMC_DISABLE; +} diff --git a/src/mainboard/google/zork/variants/morphius/Makefile.inc b/src/mainboard/google/zork/variants/morphius/Makefile.inc new file mode 100644 index 0000000000..b1212bcbdd --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +romstage-y += ./romstage.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c new file mode 100644 index 0000000000..ff8fa202fc --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +static const struct soc_amd_gpio morphius_v1_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* DMIC_AD_EN */ + PAD_GPO(GPIO_84, HIGH), +}; + +static const struct soc_amd_gpio morphius_v2_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 1) { + *size = ARRAY_SIZE(morphius_v1_gpio_set_stage_ram); + return morphius_v1_gpio_set_stage_ram; + } else if (board_version <= 2) { + *size = ARRAY_SIZE(morphius_v2_gpio_set_stage_ram); + return morphius_v2_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/ec.h b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h new file mode 100644 index 0000000000..e177507e22 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/ec.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> + +/* Enable PS/2 Mouse */ +#define SIO_EC_ENABLE_PS2M diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h b/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h b/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb new file mode 100644 index 0000000000..b4a801566e --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "20000" #mw + register "fast_ppt_limit" = "24000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "12000" #mw + + register "telemetry_vddcr_vdd_slope" = "78289" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "24519" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 42, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7375L"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "120" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/morphius/romstage.c b/src/mainboard/google/zork/variants/morphius/romstage.c new file mode 100644 index 0000000000..876b836adc --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +#include <gpio.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <delay.h> + +void variant_romstage_entry(void) +{ + //SET WIFI_PCIE_RESET_L HIGH + gpio_set(WIFI_PCIE_RESET_L, 1); + + /* Power the wifi card */ + /* wait 10ms to discharge EN_PWR_WIFI to 0V */ + mdelay(10); + gpio_set(EN_PWR_WIFI, 1); + + /* SET WIFI_PCIE_RESET_L LOW */ + gpio_set(WIFI_PCIE_RESET_L, 0); + + /* Qualcomm Atheros NFA344A needs at least 10ms delay */ + mdelay(10); + + /* SET WIFI_PCIE_RESET_L HIGH */ + gpio_set(WIFI_PCIE_RESET_L, 1); +} + +static const struct soc_amd_gpio morphius_gpio_set_wifi[] = { + /* EN_PWR_WIFI - Power off. Pull high in romstage.c */ + PAD_GPO(GPIO_29, LOW), +}; + +const struct soc_amd_gpio *variant_wifi_romstage_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(morphius_gpio_set_wifi); + return morphius_gpio_set_wifi; +} diff --git a/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc new file mode 100644 index 0000000000..4f0929f422 --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/spd/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Ordered List of APCB entries, up to 16. +# Entries should match this pattern {NAME}_x{1,2} +# There should be a matching SPD hex file in SPD_SOURCES_DIR +# matching the pattern {NAME}.spd.hex +# The _x{1,2} suffix denotes single or dual channel +# Alternatively, generated APCBs stored at +# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included. +APCB_SOURCES = samsung-K4AAG165WA-BCWE_x2 # 0b0000 +APCB_SOURCES += empty # 0b0001 +# b/149596178: We can't use dual channel channel until the PSP supports missing +# channels. +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0010 +APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0011 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100 +APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101 +APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110 +APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111 +APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000 +APCB_SOURCES += empty # 0b1001 +APCB_SOURCES += empty # 0b1010 +APCB_SOURCES += empty # 0b1011 +APCB_SOURCES += empty # 0b1100 +APCB_SOURCES += empty # 0b1101 +APCB_SOURCES += empty # 0b1110 diff --git a/src/mainboard/google/zork/variants/trembyle/Makefile.inc b/src/mainboard/google/zork/variants/trembyle/Makefile.inc new file mode 100644 index 0000000000..0b6bc4b349 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ../baseboard/spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/trembyle/gpio.c b/src/mainboard/google/zork/variants/trembyle/gpio.c new file mode 100644 index 0000000000..7973858d5e --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/gpio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +static const struct soc_amd_gpio trembyle_v1_v2_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* DMIC_AD_EN */ + PAD_GPO(GPIO_84, HIGH), +}; + +static const struct soc_amd_gpio trembyle_v3_gpio_set_stage_ram[] = { + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= 2) { + *size = ARRAY_SIZE(trembyle_v1_v2_gpio_set_stage_ram); + return trembyle_v1_v2_gpio_set_stage_ram; + } else if (board_version <= 3) { + *size = ARRAY_SIZE(trembyle_v3_gpio_set_stage_ram); + return trembyle_v3_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl new file mode 100644 index 0000000000..8177a9df2a --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/sleep.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb new file mode 100644 index 0000000000..46fada9f5f --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit" = "25000" #mw + register "fast_ppt_limit" = "30000" #mw + register "slow_ppt_time_constant" = "5" #second + register "stapm_time_constant" = "200" #second + register "sustained_power_limit" = "15000" #mw + + register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 21, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 76, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 37, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.3 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""AR Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB 3.1 + device pci 0.4 on end # USB 3.1 + end + device pci 14.6 off end # Non-Functional SDHCI + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "generic.wake" = "22" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/verstage.c b/src/mainboard/google/zork/verstage.c new file mode 100644 index 0000000000..7bfc10782a --- /dev/null +++ b/src/mainboard/google/zork/verstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/gpio_banks.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> + +static void setup_gpio(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + printk(BIOS_DEBUG, "Setting GPIOs\n"); + gpios = variant_romstage_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + printk(BIOS_DEBUG, "GPIOs setup\n"); +} + +static void setup_i2c(void) +{ + printk(BIOS_DEBUG, "Setting up i2c\n"); + i2c_soc_early_init(); + printk(BIOS_DEBUG, "i2c setup\n"); +} + +void verstage_mainboard_early_init(void) +{ + setup_gpio(); +} + +void verstage_mainboard_init(void) +{ + setup_i2c(); +} |