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-rw-r--r--src/mainboard/amd/rumba/auto.c1
-rw-r--r--src/northbridge/amd/gx2/raminit.c16
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c113
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_smbus.c2
4 files changed, 122 insertions, 10 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 6b3586b205..72d1ef4e0e 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -65,7 +65,6 @@ static void main(unsigned long bist)
cs5535_early_setup();
pll_reset();
- //msr_init();
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 67f5930496..95ce72a10e 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -18,7 +18,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 1. Initialize GLMC registers base on SPD values,
* Hard coded as XpressROM for now */
- print_debug("sdram_enable step 1\r\n");
+ //print_debug("sdram_enable step 1\r\n");
msr = rdmsr(0x20000018);
msr.hi = 0x10076013;
msr.lo = 0x00003000;
@@ -39,13 +39,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(0x2000001a);
msr.lo = 0x0101;
wrmsr(0x2000001a, msr);
- print_debug("sdram_enable step 2\r\n");
+ //print_debug("sdram_enable step 2\r\n");
/* 3. release CKE mask to enable CKE */
msr = rdmsr(0x2000001d);
msr.lo &= ~(0x03 << 8);
wrmsr(0x2000201d, msr);
- print_debug("sdram_enable step 3\r\n");
+ //print_debug("sdram_enable step 3\r\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
@@ -56,7 +56,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(0x01 << 3);
wrmsr(0x20000018, msr);
}
- print_debug("sdram_enable step 4\r\n");
+ //print_debug("sdram_enable step 4\r\n");
/* 5. set refresh interval */
msr = rdmsr(0x20000018);
@@ -68,7 +68,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo &= ~(0x03 << 6);
msr.lo |= (0x00 << 6);
wrmsr(0x20000018, msr);
- print_debug("sdram_enable step 5\r\n");
+ //print_debug("sdram_enable step 5\r\n");
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
@@ -76,7 +76,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 28) | 0x01);
wrmsr(0x20000018, msr);
- print_debug("sdram_enable step 6\r\n");
+ //print_debug("sdram_enable step 6\r\n");
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
@@ -86,7 +86,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
wrmsr(0x20000018, msr);
- print_debug("sdram_enable step 7\r\n");
+ //print_debug("sdram_enable step 7\r\n");
/* 8. load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(0x20000018);
@@ -94,7 +94,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
wrmsr(0x20000018, msr);
msr.lo &= ~0x01;
wrmsr(0x20000018, msr);
- print_debug("sdram_enable step 8\r\n");
+ //print_debug("sdram_enable step 8\r\n");
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
new file mode 100644
index 0000000000..ae3b7df441
--- /dev/null
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -0,0 +1,113 @@
+/*
+ *
+ * cs5535_early_setup.c: Early chipset initialization for CS5535 companion device
+ *
+ *
+ * This file implements the initialization sequence documented in section 4.2 of
+ * AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
+ *
+ */
+
+#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */
+#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
+
+/**
+ * @brief Setup PCI IDSEL for CS5535
+ *
+ *
+ */
+
+static void cs5535_setup_extmsr(void)
+{
+ msr_t msr;
+
+ /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
+ msr.hi = msr.lo = 0x00000000;
+ if (CS5535_GLINK_PORT_NUM <= 4) {
+ msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
+ } else {
+ msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
+ }
+ wrmsr(0x5000201e, msr);
+}
+
+static void cs5535_setup_idsel(void)
+{
+ /* write IDSEL to the write once register at address 0x0000 */
+ outl(0x1 << (CS5535_DEV_NUM + 10), 0);
+}
+
+static int cs5535_setup_iobase(void)
+{
+ msr_t msr;
+
+ /* setup LBAR for SMBus controller */
+ __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001);
+ /* setup LBAR for GPIO */
+ __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001);
+ /* setup LBAR for MFGPT */
+ __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001);
+ /* setup LBAR for ACPI */
+ __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001);
+ /* setup LBAR for MFGPT */
+ __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001);
+}
+
+static void cs5535_setup_gpio(void)
+{
+ uint32_t val;
+
+ /* setup GPIO pins 14/15 for SDA/SCL */
+ val = (1<<14 | 1<<15);
+ /* Output Enable */
+ outl(0x3fffc000, 0x6100 + 0x04);
+ //outl(val, 0x6100 + 0x04);
+ /* Output AUX1 */
+ outl(0x3fffc000, 0x6100 + 0x10);
+ //outl(val, 0x6100 + 0x10);
+ /* Input Enable */
+ //outl(0x0f5af0a5, 0x6100 + 0x20);
+ outl(0x3fffc000, 0x6100 + 0x20);
+ //outl(val, 0x6100 + 0x20);
+ /* Input AUX1 */
+ //outl(0x3ffbc004, 0x6100 + 0x34);
+ outl(0x3fffc000, 0x6100 + 0x34);
+ //outl(val, 0x6100 + 0x34);
+}
+
+static void cs5535_setup_cis_mode(void)
+{
+ msr_t msr;
+
+ /* setup CPU interface serial to mode C on both sides */
+ msr = __builtin_rdmsr(0x51000010);
+ msr.lo &= ~0x18;
+ msr.lo |= 0x10;
+ __builtin_wrmsr(0x51000010, msr.lo, msr.hi);
+ __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000);
+}
+
+static void dummy(void)
+{
+}
+
+static int cs5535_early_setup(void)
+{
+ msr_t msr;
+
+ cs5535_setup_extmsr();
+
+ msr = rdmsr(0x4c000014);
+ if (msr.lo & (0x3f << 26)) {
+ /* PLL is already set and we are reboot from PLL reset */
+ print_debug("reboot from BIOS reset\n\r");
+ return;
+ }
+ cs5535_setup_idsel();
+ cs5535_setup_iobase();
+ cs5535_setup_gpio();
+ cs5535_setup_cis_mode();
+ cs5535_enable_smbus();
+ //get_memory_speed();
+ dummy();
+}
diff --git a/src/southbridge/amd/cs5535/cs5535_early_smbus.c b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
index b7dd436887..adc4c5e090 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_smbus.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_smbus.c
@@ -11,7 +11,7 @@ static int cs5535_enable_smbus(void)
/* Set SCL freq and enable SMB controller */
val = inb(SMBUS_IO_BASE + SMB_CTRL2);
- val |= ((0x7F << 1) | SMB_CTRL2_ENABLE);
+ val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
outb(val, SMBUS_IO_BASE + SMB_CTRL2);
/* Setup SMBus host controller address to 0xEF */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 07:17:33 +0000