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-rw-r--r--src/soc/amd/stoneyridge/southbridge.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 35cf253b7b..40e69dbbad 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -429,27 +429,27 @@ static uintptr_t sb_spibase(void)
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
{
uintptr_t base = sb_spibase();
- write16((void *)base + SPI100_SPEED_CONFIG,
+ write16((void *)(base + SPI100_SPEED_CONFIG),
(norm << SPI_NORM_SPEED_NEW_SH) |
(fast << SPI_FAST_SPEED_NEW_SH) |
(alt << SPI_ALT_SPEED_NEW_SH) |
(tpm << SPI_TPM_SPEED_NEW_SH));
- write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100);
+ write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
}
void sb_disable_4dw_burst(void)
{
uintptr_t base = sb_spibase();
- write16((void *)base + SPI100_HOST_PREF_CONFIG,
- read16((void *)base + SPI100_HOST_PREF_CONFIG)
+ write16((void *)(base + SPI100_HOST_PREF_CONFIG),
+ read16((void *)(base + SPI100_HOST_PREF_CONFIG))
& ~SPI_RD4DW_EN_HOST);
}
void sb_read_mode(u32 mode)
{
uintptr_t base = sb_spibase();
- write32((void *)base + SPI_CNTRL0,
- (read32((void *)base + SPI_CNTRL0)
+ write32((void *)(base + SPI_CNTRL0),
+ (read32((void *)(base + SPI_CNTRL0))
& ~SPI_READ_MODE_MASK) | mode);
}