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-rw-r--r--src/soc/intel/cannonlake/chip.h6
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c4
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 350217807c..3a723d2ab0 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -296,6 +296,12 @@ struct soc_intel_cannonlake_config {
uint8_t SlowSlewRateForGt;
uint8_t SlowSlewRateForSa;
uint8_t SlowSlewRateForFivr;
+
+ /* DMI Power Optimizer */
+ uint8_t dmipwroptimize;
+
+ /* SATA Power Optimizer */
+ uint8_t satapwroptimize;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a9326a41bf..78b27e9514 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -221,6 +221,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
+
+ /* Power Optimizer */
+ params->PchPwrOptEnable = config->dmipwroptimize;
+ params->SataPwrOptEnable = config->satapwroptimize;
}
/* Mainboard GPIO Configuration */