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-rw-r--r--src/soc/intel/skylake/acpi/globalnvs.asl3
-rw-r--r--src/soc/intel/skylake/acpi/pch.asl5
-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h3
3 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 8a7606c6ec..5564f02df2 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -67,6 +67,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap
U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap
UIOR, 8, // 0x42 - UART debug controller init on S3 resume
+ EPCS, 8, // 0x43 - SGX Enabled status
+ EMNA, 64, // 0x44 - 0x4B EPC base address
+ ELNG, 64, // 0x4C - 0x53 EPC Length
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 03c2570a44..e40dd6b291 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -72,3 +72,8 @@ Method (_OSC, 4)
Return (Arg3)
}
}
+
+/* SGX */
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
+#include <soc/intel/common/acpi/sgx.asl>
+#endif
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 8272336e87..498bb2b184 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -58,6 +58,9 @@ typedef struct {
u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */
u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */
u8 uior; /* 0x42 - UART debug controller init on S3 resume */
+ u8 ecps; /* 0x43 - SGX Enabled status */
+ u64 emna; /* 0x44 - 0x4B EPC base address */
+ u64 elng; /* 0x4C - 0x53 EPC Length */
u8 unused[189];
/* ChromeOS specific (0x100 - 0xfff) */